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| 1996 data sheet the m pd70325 (v25+) is a single-chip microcontroller on which 16-bit cpu, ram, serial interface, timer, dma controller, interrupt controller, etc. are all integrated. the m pd70325 is software compatible with the 16/8-bit single- chip microcontroller m pd70320 (v25 tm ). the v25+ greatly improves the dma responsivity and transfer rate compared to the v25. features ? software compatible with v25 ? software compatible with m pd70108/70116 (in native mode) (some instructions added) ? internal 16-bit architecture and external 8-bit data bus ? 3-stage pipeline method ? minimum instruction cycle : 250 ns/8 mhz (external 16 mhz) : 200 ns/10 mhz (external 20 mhz) ? memory space 1 mbyte ? on-chip ram : 256 words 8 bits ? register bank (memory mapped method) : 8 banks ? input port (port t) with comparator : 8 bits ? i/o lines (input port : 4 bits, input/output ports : 20 bits) ? serial interface : 2 channels ? internal dedicated baud rate generator ? asynchronous mode and i/o interface mode ? interrupt controller ? programmable priority (8 levels) ? 3 types of interrupt response method vectored interrupt function, register bank switching function, macro service function ? dram and pseudo sram refreshing function ? dma controller : 2 channels ? 4 types of dma transfer mode ? transfer rate maximum 4 mbytes/second (when stop control is not executed by dmarq pin in demand release mode) maximum 2 mbytes/second (when stop control is executed by dmarq pin in demand release mode, or burst mode) ? address pointer (linear) : 20 bits ? terminal counter : 16 bits ? 16-bit timer : 2 channels ? time base counter (20 bits) : 1 channel ? on-chip clock generator ? programmable wait function ? standby function (stop, halt) mos integrated circuit v25+ tm 16/8-bit single-chip microcontroller the information in this document is subject to change without notice. the mark shows major revised points. m pd70325 1995 document no. u12850ej7v0ds00 (7th edition) date published november 1997 n printed in japan www.datasheet.co.kr datasheet pdf - http://www..net/
2 m pd70325 ordering information part number package external clock (mhz) m pd70325gj-8-5bg 94-pin plastic qfp (20 20 mm) 16 m pD70325GJ-10-5bg 94-pin plastic qfp (20 20 mm) 20 m pd70325l-8 84-pin plastic qfj (1150 1150 mil) 16 m pd70325l-10 84-pin plastic qfj (1150 1150 mil) 20 www.datasheet.co.kr datasheet pdf - http://www..net/ 3 m pd70325 comparison between v25 and v25+ v25 v35 tm v25+ v35+ tm m pd70320 m pd70330 m pd70325 m pd70335 transfer processing method depends on microprogram depends on dedicated hardware maximum transfer rate (8-mhz 0.6 mbytes/second 0.8 mbytes/second 4 mbytes/second 5.3 mbytes/second operation) sampling timing of dma request between instruction execution cycles between bus cycles dma service channel in on-chip ram area in special function register specification method of transfer address segment method linear method execution format in single-step mode 1 dma transfer/1 instruction execution 1 dma transfer/1 bus cycle interrupt request during dma transfer accepts only nmi not accepted (demand release mode) number of necessary waits when not necessary 2 waits stop is controlled by dmarq (demand release mode) transfer processing units byte/word byte/word byte byte/word tc (terminal counter) setting value number of times of dma transfer (number of times of dma transfer) C 1 generation timing of terminal counter tc = 0 tc = ffffh tc output low-level width fixed expanded by wait insertion transmit clock output in not available available (sck0 pin) asynchronous mode (channel 0) serial error register yes serial status register receive buffer full flag no in serial status register transmit buffer empty flag no in serial status register all sent flag no in serial status register interrupt source register no yes external data bus 8 bits 16 bits 8 bits 16 bits maximum operating frequency 8 mhz 10 mhz dma function serial interface interrupt function www.datasheet.co.kr datasheet pdf - http://www..net/ 4 m pd70325 pin configuration (top view) 94-pin plastic qfp m pd70325gj-8-5bg m pD70325GJ-10-5bg remarks 1. nc : non-connection 2. ic : internally connected cautions 1. fix ic pin individually to high level via a pull-up resistor externally. 2. fix ea pin to low level. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 a11 nc a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 p07/clkout p06 74 73 72 32 31 30 29 28 27 26 25 24 ic p23/dmarq1 p24/dmaak1 p25/tc1 p26/hldak p27/hldrq nmi (p10) p11/intp0 p12/intp1 p13/intp2/intak p14/int/poll p15/tout p16/sck0 p17/ready pt0 pt1 pt2 pt3 pt4 pt5 nc pt6 pt7 ic a12 nc a13 a14 a15 a16 a17 a18 a19 rxd0 gnd cts0 txd0 rxd1 cts1 txd1 p20/dmarq0 ic v dd v dd p21/dmaak0 nc p22/tc0 p05 nc ic p04 p03 p02 p01 p00 ea mreq iostb mstb r/w refrq reset v dd v dd x2 x1 gnd gnd nc nc v th www.datasheet.co.kr datasheet pdf - http://www..net/ 5 m pd70325 84-pin plastic qfj m pd70325l-8 m pd70325l-10 remark ic: internally connected cautions 1. fix ic pin individually to high level via a pull-up resistor externally. 2 fix ea pin to low level. 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p07/clkout d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 a12 a13 a14 a15 a16 a17 a18 a19 rxd0 gnd cts0 txd0 rxd1 cts1 txd1 p20/dmarq0 ic v dd p21/dmaak0 p22/tc0 ic pt7 pt6 pt5 pt4 pt3 pt2 pt1 pt0 p17/ready p16/sck0 p15/tout p14/int/poll p13/intp2/intak p12/intp1 p11/intp0 nmi (p10) p27/hldrq p26/hldak p25/tc1 p24/dmaak1 p23/dmarq1 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 p06 p05 ic p04 p03 p02 p01 p00 ea mreq iostb mstb r/w refrq reset v dd x2 x1 gnd v th ic www.datasheet.co.kr datasheet pdf - http://www..net/ 6 m pd70325 note the internal rom of 8 kbytes is reserved for specific use such as testing and not user-accessible. internal block diagram p20/dmarq0 p21/dmaak0 p22/tc0 p23/dmarq1 p24/dmaak1 p25/tc1 txd0 rxd0 p16/sck0 cts0 txd1 rxd1 cts1 nmi (p10) p11/intp0 p12/intp1 p13/intp2/intak p14/int/poll a0 to a19 reset hldak/p26 hldrq/p27 ready/p17 mreq mstb r/w iostb poll/int/p14 ea d0 to d7 x1 x2 v dd gnd bus control logic staging latch staging latch programmable dma controller serial interface baud rate generator programmable interrupt controller instruction decoder micro sequenser micro rom alu lc etc. psw pc ta tb tc internal ram 256 byte ? gr ? macro service channel queue (6 byte) 16-bit timer time base counter port port with comparator cg tout/p15 clkout/p07 p0 p1 p2 pt0 to 7 v th refrq adm internal rom note 8 kbyte (reserved) pfp inc www.datasheet.co.kr datasheet pdf - http://www..net/ 7 m pd70325 contents 1. pin functions ............................................................................................................... ................... 8 1.1 port pins ................................................................................................................... .................................... 8 1.2 non-port pins ............................................................................................................... ................................ 9 2. instruction sets ............................................................................................................ ............. 10 2.1 comparison between m pd70108 and 70116 ........................................................................................... 10 2.2 instruction set operation ................................................................................................... ...................... 12 2.3 instruction set table ....................................................................................................... .......................... 16 2.4 number of clocks table ...................................................................................................... ..................... 38 3. electrical specifications ................................................................................................... ... 49 4. package drawings ............................................................................................................ ......... 74 5. recommended soldering conditions ................................................................................ 76 www.datasheet.co.kr datasheet pdf - http://www..net/ 8 m pd70325 1. pin functions 1.1 port pins pin name input/output port function control function p00 to p06 input & output 8-bit input/output ports, each to p07/clkout input & output/output be specified bit-by-bit system clock output nmi (p10) input used as non-maskable interrupt request input (input port) p11/intp0 used as both external interrupt p12/intp1 request input and input port p13/intp2/intak input/input/output int acknowledge signal output p14/poll/int input & output/input/input used as both specifiable input/ external interrupt request input output port and poll input p15/tout input & output/output input/output port specifiable timer output p16/sck0 bit-by-bit serial clock output p17/ready input & output/input ready input p20/dmarq0 input & output/input 8-bit input/output port specifiable dma request input (ch0) p21/dmaak0 input & output/input bit-by-bit dma acknowledge output (ch0) p22/tc0 dma end output (ch0) p23/dmarq1 input & output/input dma request input (ch1) p24/dmaak1 input & output/output dma acknowledge output (ch1) p25/tc1 dma end output (ch1) p26/hldak input & output/output hold acknowledge output p27/hldrq input & output/input hold input pt0 to pt7 input 8-bit input port with comparator remark all port pins become input ports after reset is released. when using p13/intp2/intak as a intak pin, be sure to pull up the pin to avoid a malfunction of external interrupt controller after reset is released. www.datasheet.co.kr datasheet pdf - http://www..net/ 9 m pd70325 1.2 non-port pins pin name input/output function txd0 output serial data output txd1 rxd0 input serial data input rxd1 cts0 input & output cts input in asynchronous mode, receive clock input/output in i/o interface mode cts1 input cts input refrq output dram refresh pulse output v th input comparator reference voltage input reset reset signal input ea fix to low level x1 used to connect crystal resonator for oscillating system clock. x2 external clock is entered by entering reverse phase clock to both x1 and x2 pins. d0 to d7 input & output 8-bit data bus a0 to a19 output 20-bit address output mreq output used to indicate that memory bus cycle has been started mstb memory read/memory write strobe output r/ w read cycle/write cycle id signal output iostb i/o read/i/o write strobe output v dd positive power supply pins (all pins should be connected) gnd gnd pins (all pins should be connected) ic internally connected (fix to high level via a pull-up resistor externally) www.datasheet.co.kr datasheet pdf - http://www..net/ 10 m pd70325 2. instruction sets the m pd70325 instruction sets are compatible with those of m pd70320. 2.1 comparison between m pd70108 and 70116 the m pd70325 instruction sets are upward-compatible with those of m pd70108/70116 in native mode. the following instructions are newly added to the m pd70108/70116. (1) conditional branch instruction ? btclr bit test instruction used for special function registers if, when this btclr is executed, the target special function register bit status is 1, the bit is reset (0) and the program is branched to short-label described in the operand. if the target bit status is 0, the program is moved to the next instruction. psw is not changed in this instruction. (descriptive format) operand mnemonic special function special function register address register bit branch address btclr sfr imm3 short-label (2) interrupt instructions ? retrbi return instruction used for register banks this instruction is used to return the program from the interrupt service routine in which the register bank switching function is used. it cannot be used for returning from vectored interrupt servicing. (descriptive format) mnemonic operand retrbi none ? fint this instruction is used to report the interrupt controller that interrupt servicing has ended. if an interrupt other than nmi, int, and software interrupt is used, this instruction must be executed prior to the instruction for returning from interrupt servicing. it should not be used for nmi, int and software interrupts. (descriptive format) (3) cpu instruction ? stop instruction for transition to stop state (descriptive format) mnemonic operand fint none mnemonic operand stop none www.datasheet.co.kr datasheet pdf - http://www..net/ 11 m pd70325 (4) register bank switch instructions ? brkcs used to switch register banks a register bank is switched to the register bank indicated by the lower 3 bits in the 16-bit register described in the operand. the program is also branched with this instruction to the address obtained from the ps stored in advance in the new register bank and the vector pc. the retrbi instruction is used to return the program from the new register bank. (descriptive format) ? tsksw used to switch register banks just like the brkcs instruction, this instruction is also executed to select a register bank. the program is branched to the address obtained from the ps stored in advance in the new register bank and the address obtained from the pc save area. (descriptive format) (5) data transfer instructions ? movspa used to transfer ss and sp values this instruction is executed to transfer both ss and sp values before the register bank is switched to ss and sp of the current (post-switching) register bank. (descriptive format) ? movspb used to transfer ss and sp values this instruction is executed to transfer the ss and sp values of the current (pre-switching) register bank to the ss and sp of the new register bank indicated by the lower 3 bits in the 16- bit register described in the operand. (descriptive format) some m pd70108/ 70116 instructions should be much cared as shown below when used for the m pd70325. ? i/o instruction, primitive i/o instruction if psw ibrk flag is reset (0), an interrupt is generated without executing this instruction. be sure to set (1) the ibrk flag when using the i/o instruction. ? fpo instruction an interrupt is generated without executing this instruction. mnemonic operand brkcs reg16 mnemonic operand tsksw reg16 mnemonic operand movspa none mnemonic operand movspb reg16 www.datasheet.co.kr datasheet pdf - http://www..net/ 12 m pd70325 2.2 instruction set operation table 2-1. operand identifier identifier description reg, reg 8-/16-bit general register reg8, reg8 8-bit general register reg16, reg16 16-bit general register dmem 8-/16-bit memory location mem 8-/16-bit memory location mem8 8-bit memory location mem16 16-bit memory location mem32 32-bit memory location sfr 8-bit special function register location imm constant within 0 to ffffh imm3 constant within 0 to 7 imm4 constant within 0 to fh imm8 constant within 0 to ffh imm16 constant within 0 to ffffh acc register aw or al sreg segment register src-table 256-byte conversion table name src-block register ix-addressed block name dst-block register iy-addressed block name near-proc procedure in the current program segment far-proc procedure in another program segment near-label label in the current program segment short-label label within end of instruction to C128 to +127 bytes far-label label in another program segment memptr16 word including location offset in the current program segment to which control is to be passed memptr32 double-word including location offset in another program segment to which control is to be passed and segment base address regptr16 16-bit general register including location offset in another program segment to which control is to be passed pop-value number of bytes to be abandoned from stack (0 to 64k, normally even number) fp-op immediate value to judge instruction code of external floating point operation chip r register set www.datasheet.co.kr datasheet pdf - http://www..net/ 13 m pd70325 identifier description w byte/word specification bit (0: byte, 1: word). however, when s = 1, the sign extended byte data should be 16-bit operand even when w is 1. reg, reg register field (000 to 111) mem memory field (000 to 111) mod mode field (00 to 10) s sign extension specification bit (0: sign is not extended, 1: sign is extended) x, xxx, yyy, zzz data used to judge instruction code of external floating-point operation chip table 2-2. operation code identifier table 2-3. operation identifier (1/2) identifier description aw accumulator (16 bits) ah accumulator (upper byte) al accumulator (lower byte) bw register bw (16 bits) cw register cw (16 bits) cl register cw (lower byte) dw register dw (16 bits) sp stack pointer (16 bits) pc program counter (16 bits) psw program status word (16 bits) ix index register (source) (16 bits) iy index register (destination) (16 bits) ps program segment register (16 bits) ds1 data segment 1 register (16 bits) ds0 data segment 0 register (16 bits) ss stack segment register (16 bits) ac auxiliary carry flag cy carry flag p parity flag s sign flag z zero flag dir direction flag ie interrupt enable flag v overflow flag brk break flag () contents in memory shown in ( ) disp displacement (8/16 bits) ext-disp8 16 bits obtained by extending sign of 8-bit displacement www.datasheet.co.kr datasheet pdf - http://www..net/ 14 m pd70325 table 2-3. operation identifier (2/2) identifier description temp temporary register (8/16/32 bits) tmpcy temporary carry flag (1 bit) seg immediate segment data (16 bits) offset immediate offset data (16 bits) ? transfer direction + addition C subtraction multiplication ? division % modulo and or exclusive or h 2-digit hexadecimal number h 4-digit hexadecimal number identifier description (blank) no change 0 cleared to 0 1 set to 1 set or cleared according to the result u not defined r the previously saved value is restored. table 2-4. flag operation identifier table 2-5. memory addressing 0 0 0 1 1 0 0 0 0 bw + ix bw + ix + disp 8 bw + ix + disp 16 0 0 1 bw + iy bw + iy + disp 8 bw + iy + disp 16 0 1 0 bp + ix bp + ix + disp 8 bp + ix + disp 16 0 1 1 bp + iy bp + iy + disp 8 bp + iy + disp 16 1 0 0 ix ix + disp 8 ix + disp 16 1 0 1 iy iy + disp 8 iy + disp 16 1 1 0 direct address bp + disp 8 bp + disp 16 1 1 1 bw bw + disp 8 bw + disp 16 mod mem www.datasheet.co.kr datasheet pdf - http://www..net/ 15 m pd70325 table 2-6. 8/16-bit general register selection table 2-7. segment register selection reg, reg w = 0 w = 1 000 al aw 001 cl cw 010 dl dw 011 bl bw 100 ah sp 101 ch bp 110 dh ix 111 bh iy sreg 00 ds1 01 ps 10 ss 11 ds0 www.datasheet.co.kr datasheet pdf - http://www..net/ 16 m pd70325 2.3 instruction set table data transfer mov ldea trans xch movspa note movspb note reg,reg mem,reg reg,mem mem,imm reg,imm acc,dmem dmem,acc sreg,reg16 sreg,mem16 reg16,sreg mem16,sreg ds0,reg16, mem32 ds1,reg16, mem32 ah,psw psw,ah reg16,mem16 src-table reg,reg mem,reg reg,mem aw,reg16 reg16,aw reg16 operation code 1 0 0 0 1 0 1 w 1 0 0 0 1 0 0 w 1 0 0 0 1 0 1 w 1 1 0 0 0 1 1 w 1 0 1 1 w reg 1 0 1 0 0 0 0 w 1 0 1 0 0 0 1 w 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 0 0 1 1 0 1 1 1 0 1 0 1 1 1 1 0 0 0 0 1 1 w 1 0 0 0 0 1 1 w 1 0 0 1 0 reg 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 reg 7 6 5 4 3 2 1 0 1 1 reg reg mod reg mem mod reg mem mod 0 0 0 mem 1 1 0 sreg reg mod 0 sreg mem 1 1 0 sreg reg mod 0 sreg mem mod reg mem mod reg mem mod reg mem 1 1 reg reg mod reg mem 0 0 1 0 0 1 0 1 1 0 0 1 0 1 0 1 7 6 5 4 3 2 1 0 group mnemonic operand 2 2 to 4 2 to 4 3 to 6 2 to 3 3 3 2 2 to 4 2 2 to 4 2 to 4 2 to 4 1 1 2 to 4 1 2 2 to 4 1 2 3 bytes flags ac cy v p s z reg reg (mem) reg reg (mem) (mem) imm reg imm when w = 0, al (dmem) when w = 1, ah (dmem + 1), al (dmem) when w = 0, (dmem) al when w = 1, (dmem + 1) ah, (dmem) al sreg reg16 sreg (mem16) reg16 sreg (mem16) sreg reg16 (mem32) ds0 (mem32 + 2) reg16 (mem32) ds1 (mem32 + 2) ah s, z, f1, ac, f0, p, ibrk, cy s, z, f1, ac, f0, p, ibrk, cy ah reg16 mem16 al (bw + al) reg reg (mem) reg aw reg16 new register bank ss and sp old register bank ss and sp ss and sp of reg16-indicated new register bank old register bank ss and sp operation sreg : ss, ds0, ds1 sreg : ss, ds0, ds1 note these instructions are newly added to the pd70108/70116. m www.datasheet.co.kr datasheet pdf - http://www..net/ 17 m pd70325 repc repnc rep repe repz repne repnz movbk cmpbk cmpm ldm stm dst-block, src-block src-block, dst-block dst-block src-block dst-block operation code 0 1 1 0 0 1 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 0 1 0 1 0 0 1 0 w 1 0 1 0 0 1 1 w 1 0 1 0 1 1 1 w 1 0 1 0 1 1 0 w 1 0 1 0 1 0 1 w 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 group mnemonic operand 1 1 1 1 1 1 1 1 1 bytes flags ac cy v p s z executes the primitive block transfer instruction in the continued byte while cw 0, and decrements cw by one. if any interruption is held at this time, it is processed. the program exits the loop when cy 1. same as above. the program exits the loop when cy 0. executes the primitive block transfer instruction in the continued byte while cw 0, and decrements cw by one. if any interruption is held at this time, it is processed. the program exits the loop when the primitive block transfer instruction is cmpbk or cmpm, and when z 1. same as above. the program exits the loop when z 0. when w = 0, (iy) (ix) dir = 0: ix ix + 1, iy iy + 1 dir = 1: ix ix C 1, iy iy C 1 when w = 1, (iy + 1, iy) (ix + 1, ix) dir = 0: ix ix + 2, iy iy + 2 dir = 1: ix ix C 2, iy iy C 2 when w = 0, (ix) C (iy) dir = 0: ix ix + 1, iy iy + 1 dir = 1: ix ix C 1, iy iy C 1 when w = 1, (ix + 1, ix) C (iy + 1, iy) dir = 0: ix ix + 2, iy iy + 2 dir = 1: ix ix C 2, iy iy C 2 when w = 0, al C (iy) dir = 0: iy iy + 1; dir = 1: iy iy C 1 when w = 1, aw C (iy + 1, iy) dir = 0: iy iy + 2; dir = 1: iy iy C 2 when w = 0, al (ix) dir = 0: ix ix + 1; dir = 1: ix ix C 1 when w = 1, aw (ix + 1, ix) dir = 0: ix + 2; dir = 1: ix ix C 2 when w = 0, (iy) al dir = 0: iy iy + 1; dir = 1: iy iy C 1 when w = 1, (iy + 1, iy) aw dir = 0: iy iy + 2; dir = 1: iy iy C 2 operation repeat prefix primitive block transfer www.datasheet.co.kr datasheet pdf - http://www..net/ 18 m pd70325 ins ext in out inm outm reg8,reg8 reg8,imm4 reg8,reg8 reg8,imm4 acc,imm8 acc,dw imm8,acc dw,acc dst-block,dw dw,src-block operation code 0 0 0 0 1 1 1 1 1 1 reg reg 0 0 0 0 1 1 1 1 1 1 0 0 0 reg 0 0 0 0 1 1 1 1 1 1 reg reg 0 0 0 0 1 1 1 1 1 1 0 0 0 reg 1 1 1 0 0 1 0 w 1 1 1 0 1 1 0 w 1 1 1 0 0 1 1 w 1 1 1 0 1 1 1 w 0 1 1 0 1 1 0 w 0 1 1 0 1 1 1 w 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 group mnemonic operand 3 4 3 4 2 1 2 1 1 1 bytes flags ac cy v p s z 16-bit field aw 16-bit field aw aw 16-bit field aw 16-bit field when w = 0, al (imm8) when w = 1, ah (imm8 + 1), al (imm8) when w = 0, al (dw) when w = 1, ah (dw + 1), al (dw) when w = 0, (imm8) al when w = 1, (imm8 + 1) ah, (imm8) al when w = 0, (dw) al when w = 1, (dw + 1) ah, (dw) al when w = 0, (iy) (dw) dir = 0: iy iy + 1; dir = 1: iy iy C 1 when w = 1, (iy + 1, iy) (dw + 1, dw) dir = 0: iy iy + 2; dir = 1: iy iy C 2 when w = 0, (dw) (ix) dir = 0: ix ix + 1; dir = 1: ix ix C 1 when w = 1, (dw + 1, dw) (ix + 1, ix) dir = 0: ix ix + 2; dir = 1: ix ix C 2 operation bit field opera- tion i/o 0 0 1 1 0 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 note note note note primitive i/o note when ibrk = 0, a software interrupt is generated automatically and the instruction is not executed. www.datasheet.co.kr datasheet pdf - http://www..net/ 19 m pd70325 add addc sub subc reg,reg mem,reg reg,mem reg,imm mem,imm acc,imm reg,reg mem,reg reg,mem reg,imm mem,imm acc,imm reg,reg mem,reg reg,mem reg,imm mem,imm acc,imm reg,reg mem,reg reg,mem reg,imm mem,imm acc,imm operation code 0 0 0 0 0 0 1 w 0 0 0 0 0 0 0 w 0 0 0 0 0 0 1 w 1 0 0 0 0 0 s w 1 0 0 0 0 0 s w 0 0 0 0 0 1 0 w 0 0 0 1 0 0 1 w 0 0 0 1 0 0 0 w 0 0 0 1 0 0 1 w 1 0 0 0 0 0 s w 1 0 0 0 0 0 s w 0 0 0 1 0 1 0 w 0 0 1 0 1 0 1 w 0 0 1 0 1 0 0 w 0 0 1 0 1 0 1 w 1 0 0 0 0 0 s w 1 0 0 0 0 0 s w 0 0 1 0 1 1 0 w 0 0 0 1 1 0 1 w 0 0 0 1 1 0 0 w 0 0 0 1 1 0 1 w 1 0 0 0 0 0 s w 1 0 0 0 0 0 s w 0 0 0 1 1 1 0 w 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 group mnemonic operand 2 2 to 4 2 to 4 3 to 4 3 to 6 2 to 3 2 2 to 4 2 to 4 3 to 4 3 to 6 2 to 3 2 2 to 4 2 to 4 3 to 4 3 to 6 2 to 3 2 2 to 4 2 to 4 3 to 4 3 to 6 2 to 3 bytes flags ac cy v p s z reg reg + reg (mem) (mem) + reg reg reg + (mem) reg reg + imm (mem) (mem) + imm when w = 0, al al + imm when w = 1, aw aw + imm reg reg + reg + cy (mem) (mem) + reg + cy reg reg + (mem) + cy reg reg + imm + cy (mem) (mem) + imm + cy when w = 0, al al + imm + cy when w = 1, aw aw + imm + cy reg reg C reg (mem) (mem) C reg reg reg C (mem) reg reg C imm (mem) (mem) C imm when w = 0, al al C imm when w = 1, aw aw C imm reg reg C reg C cy (mem) (mem) C reg C cy reg reg C (mem) C cy reg reg C imm C cy (mem) (mem) C imm C cy when w = 0, al al C imm C cy when w = 1, aw aw C imm C cy operation addi- tion/ subtrac- tion 1 1 reg reg mod reg mem mod reg mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 reg reg mod reg mem mod reg mem 1 1 0 1 0 reg mod 0 1 0 mem 1 1 reg reg mod reg mem mod reg mem 1 1 1 0 1 reg mod 1 0 1 mem 1 1 reg reg mod reg mem mod reg mem 1 1 0 1 1 reg mod 0 1 1 mem www.datasheet.co.kr datasheet pdf - http://www..net/ 20 m pd70325 add4s sub4s cmp4s rol4 ror4 inc dec reg8 mem8 reg8 mem8 reg8 mem reg16 reg8 mem reg16 operation code 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 reg 0 0 0 0 1 1 1 1 mod 0 0 0 mem 0 0 0 0 1 1 1 1 1 1 0 0 0 reg 0 0 0 0 1 1 1 1 mod 0 0 0 mem 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 w 0 1 0 0 0 reg 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 w 0 1 0 0 1 reg 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 group mnemonic operand 2 2 2 3 3 to 5 3 3 to 5 2 2 to 4 1 2 2 to 4 1 bytes flags ac cy v p s z dst bcd string dst bcd string + src bcd string dst bcd string dst bcd string C src bcd string dst bcd string C src bcd string reg8 reg8 + 1 (mem) (mem) + 1 reg16 reg16 + 1 reg8 reg8 C 1 (mem) (mem) C 1 reg16 reg16 C 1 operation bcd opera- tion 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 1 reg mod 0 0 1 mem u u u u u u u u u u u u note note note incre- ment/ decre- ment al l upper byte lower byte reg al l upper byte lower byte mem al l upper byte lower byte reg al l upper byte lower byte mem note the number of bcd digits is given in the cl register. the value can be set within 1 to 254. www.datasheet.co.kr datasheet pdf - http://www..net/ 21 m pd70325 mulu mul reg8 mem8 reg16 mem16 reg8 mem8 reg16 mem16 reg16, (reg16,) note imm8 reg16, mem16, imm8 reg16, (reg16,) note imm16 reg16, mem16, imm16 operation code 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 group mnemonic operand 2 2 to 4 2 2 to 4 2 2 to 4 2 2 to 4 3 3 to 5 4 4 to 6 bytes flags ac cy v p s z aw al reg8 ah = 0: cy 0, v 0 ah 0: cy 1, v 1 aw al (mem8) ah = 0: cy 0, v 0 ah 0: cy 1, v 1 dw, aw aw reg16 dw = 0: cy 0, v 0 dw = 1: cy 1, v 1 dw, aw aw (mem16) dw = 0: cy 0, v 0 dw = 1: cy 1, v 1 aw al reg8 extension of ah = al sign: cy 0, v 0 extension of ah al sign: cy 1, v 1 aw al (mem8) extension of ah = al sign: cy 0, v 0 extension of ah al sign: cy 1, v 1 dw, aw aw reg16 extension of dw = aw sign: cy 0, v 0 extension of dw aw sign: cy 1, v 1 dw, aw aw (mem16) extension of dw = aw sign: cy 0, v 0 extension of dw aw sign: cy 1, v 1 reg16 reg16 imm8 product 16 bits: cy 0, v 0 product > 16 bits: cy 1, v 1 reg16 (mem16) imm8 product 16 bits: cy 0, v 0 product > 16 bits: cy 1, v 1 reg16 reg16 imm16 product 16 bits: cy 0, v 0 product > 16 bits: cy 1, v 1 reg16 (mem16) imm16 product 16 bits: cy 0, v 0 product > 16 bits: cy 1, v 1 operation multipli- cation 1 1 1 0 0 reg mod 1 0 0 mem 1 1 1 0 0 reg mod 1 0 0 mem 1 1 1 0 1 reg mod 1 0 1 mem 1 1 1 0 1 reg mod 1 0 1 mem 1 1 reg reg mod reg mem 1 1 reg reg mod reg mem u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u note the 2nd operand is omissible. if omitted, the 1st operand is assumed. www.datasheet.co.kr datasheet pdf - http://www..net/ 22 m pd70325 divu reg8 mem8 reg16 mem16 operation code 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 group mnemonic operand 2 2 to 4 2 2 to 4 bytes flags ac cy v p s z temp aw when temp reg8 ffh ah ? temp%reg8, al ? temp reg8 when temp reg8 > ffh (sp e 1, sp e 2) ? psw, (sp e 3, sp e 4) ? ps (sp e 5, sp e 6) ? pc, sp ? sp e 6 ie ? 0, brk ? 0, ps ? (3, 2), pc ? (1, 0) temp ? aw when temp (mem8) ffh ah ? temp%(mem8), al ? temp (mem8) when temp (mem8) > ffh (sp e 1, sp e 2) ? psw, (sp e 3, sp e 4) ? ps (sp e 5, sp e 6) ? pc, sp ? sp e 6 ie ? 0, brk ? 0, ps ? (3, 2), pc ? (1, 0) temp ? dw, aw when temp reg16 ffffh dw ? temp%reg16, aw ? temp reg16 when temp reg16 > ffffh (sp e 1, sp e 2) ? psw, (sp e 3, sp e 4) ? ps (sp e 5, sp e 6) ? pc, sp ? sp e 6 ie ? 0, brk ? 0, ps ? (3, 2), pc ? (1, 0) temp ? dw, aw when temp (mem16) ffffh dw ? temp%(mem16), aw ? temp (mem16) when temp (mem16) > ffffh (sp e 1, sp e 2) ? psw, (sp e 3, sp e 4) ? ps (sp e 5, sp e 6) ? pc, sp ? sp e 6 ie ? 0, brk ? 0, ps ? (3, 2), pc ? (1, 0) operation unsign- ed division 1 1 1 1 0 reg mod 1 1 0 mem 1 1 1 1 0 reg mod 1 1 0 mem u u u u u u u u u u u u u u u u u u u u u u u u www.datasheet.co.kr datasheet pdf - http://www..net/ 23 m pd70325 div reg8 mem8 reg16 mem16 operation code 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 group mnemonic operand 2 2 to 4 2 2 to 4 bytes flags ac cy v p s z operation signed division 1 1 1 1 1 reg mod 1 1 1 mem 1 1 1 1 1 reg mod 1 1 1 mem u u u u u u u u u u u u u u u u u u u u u u u u temp aw when temp reg8 > 0 and temp reg8 7fh or temp reg8 < 0 and temp reg8 > 0 e 7fh e 1 ah ? temp%reg8, al ? temp reg8 when temp reg8 > 0 and temp reg8 > 7fh or temp reg8 > 0 and temp reg8 < 0 e 7fh e 1 (sp e 1, sp e 2) ? psw, (sp e 3, sp e 4) ? ps (sp e 5, sp e 6) ? pc, sp ? sp e 6 ie ? 0, brk ? 0, ps ? (3, 2), pc ? (1, 0) temp ? aw when temp (mem8) > 0 and temp (mem8) 7fh or temp (mem8) < 0 and temp (mem8) > 0 e 7fh e 1 ah ? temp%(mem8), al ? temp (mem8) when temp (mem8) > 0 and temp (mem8) > 7fh or temp (mem8) > 0 and temp (mem8) < 0 e 7fh e 1 (sp e 1, sp e 2) ? psw, (sp e 3, sp e 4) ? ps (sp e 5, sp e 6) ? pc, sp ? sp e 6 ie ? 0, brk ? 0, ps ? (3, 2), pc ? (1, 0) temp ? dw, aw when temp reg16 > 0 and temp reg16 7fffh or temp reg16 < 0 and temp reg16 > 0 e 7fffh e 1 dw ? temp%reg16, aw ? temp reg16 when temp reg16 > 0 and temp reg16 > 7fffh or temp reg16 > 0 and temp reg16 < 0 e 7fffh e 1 (sp e 1, sp e 2) ? psw, (sp e 3, sp e 4) ? ps (sp e 5, sp e 6) ? pc, sp ? sp e 6 ie ? 0, brk ? 0, ps ? (3, 2), pc ? (1, 0) temp ? dw, aw when temp (mem16) > 0 and temp (mem16) 7fffh or temp (mem16) < 0 and temp (mem16) > 0 e 7fffh e 1 dw ? temp%(mem16), aw ? temp (mem16) when temp (mem16) > 0 and temp (mem16) > 7fffh or temp (mem16) > 0 and temp (mem16) < 0 e 7fffh e 1 (sp e 1, sp e 2) ? psw, (sp e 3, sp e 4) ? ps (sp e 5, sp e 6) ? pc, sp ? sp e 6 ie ? 0, brk ? 0, ps ? (3, 2), pc ? (1, 0) www.datasheet.co.kr datasheet pdf - http://www..net/ 24 m pd70325 adjba adj4a adjbs adj4s cvtbd cvtdb cvtbw cvtwl cmp not neg reg,reg mem,reg reg,mem reg,imm mem,imm acc,imm reg mem reg mem operation code 0 0 1 1 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 1 0 0 1 1 1 0 1 w 0 0 1 1 1 0 0 w 0 0 1 1 1 0 1 w 1 0 0 0 0 0 s w 1 0 0 0 0 0 s w 0 0 1 1 1 1 0 w 1 1 1 1 0 1 1 w 1 1 1 1 0 1 1 w 1 1 1 1 0 1 1 w 1 1 1 1 0 1 1 w 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 group mnemonic operand 1 1 1 1 2 2 1 1 2 2 to 4 2 to 4 3 to 4 3 to 6 2 to 3 2 2 to 4 2 2 to 4 bytes flags ac cy v p s z when al ? 0fh > 9 or ac = 1, al al + 6 ah ah + 1, ac 1, cy ac, al al ? 0fh when al ? 0fh > 9 or ac = 1, al al + 6, ac 1 when al > 9fh or cy = 1, al al + 60h, cy 1 when al ? 0fh > 9 or ac = 1, al al C 6, ah ah C 1, ac 1 cy ac, al al ? 0fh when al ? 0fh > 9 or ac = 1, al al C 6, ac 1 when al > 9fh or cy = 1, al al C 60h, cy 1 ah al 0ah, al al%0ah al ah 0ah + al, ah 0 when al < 80h, ah 0. in other cases, ah ffh. when aw < 8000h, dw 0. in other cases, dw ffffh. reg C reg (mem) C reg reg C (mem) reg C imm (mem) C imm when w = 0, al C imm when w = 1, aw C imm reg reg (mem) (mem) reg reg + 1 (mem) (mem) + 1 operation bcd adjust- ment 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 1 1 reg reg mod reg mem mod reg mem 1 1 1 1 1 reg mod 1 1 1 mem 1 1 0 1 0 reg mod 0 1 0 mem 1 1 0 1 1 reg mod 0 1 1 mem u u u u u u u u u u u u u u u u data conver- sion compare comple- ment opera- tion www.datasheet.co.kr datasheet pdf - http://www..net/ 25 m pd70325 test and or xor reg,reg mem,reg reg,mem reg,imm mem,imm acc,imm reg,reg mem,reg reg,mem reg,imm mem,imm acc,imm reg,reg mem,reg reg,mem reg,imm mem,imm acc,imm reg,reg mem,reg reg,mem reg,imm mem,imm acc,imm operation code 1 0 0 0 0 1 0 w 1 0 0 0 0 1 0 w 1 1 1 1 0 1 1 w 1 1 1 1 0 1 1 w 1 0 1 0 1 0 0 w 0 0 1 0 0 0 1 w 0 0 1 0 0 0 0 w 0 0 1 0 0 0 1 w 1 0 0 0 0 0 0 w 1 0 0 0 0 0 0 w 0 0 1 0 0 1 0 w 0 0 0 0 1 0 1 w 0 0 0 0 1 0 0 w 0 0 0 0 1 0 1 w 1 0 0 0 0 0 0 w 1 0 0 0 0 0 0 w 0 0 0 0 1 1 0 w 0 0 1 1 0 0 1 w 0 0 1 1 0 0 0 w 0 0 1 1 0 0 1 w 1 0 0 0 0 0 0 w 1 0 0 0 0 0 0 w 0 0 1 1 0 1 0 w 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 group mnemonic operand 2 2 to 4 3 to 4 3 to 6 2 to 3 2 2 to 4 2 to 4 3 to 4 3 to 6 2 to 3 2 2 to 4 2 to 4 3 to 4 3 to 6 2 to 3 2 2 to 4 2 to 4 3 to 4 3 to 6 2 to 3 bytes flags ac cy v p s z reg ? reg (mem) ? reg reg ? imm (mem) ? imm when w = 0, al ? imm8 when w = 1, aw ? imm16 reg reg ? reg (mem) (mem) ? reg reg reg ? (mem) reg reg ? imm (mem) (mem) ? imm when w = 0, al al ? imm8 when w = 1, aw aw ? imm16 reg reg M reg (mem) (mem) M reg reg reg M (mem) reg reg M imm (mem) (mem) M imm when w = 0, al al M imm8 when w = 1, aw aw M imm16 reg reg M reg (mem) (mem) M reg reg reg M (mem) reg reg M imm (mem) (mem) M imm when w = 0, al al M imm8 when w = 1, aw aw M imm16 operation logical opera- tion 1 1 reg reg mod reg mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 reg reg mod reg mem mod reg mem 1 1 1 0 0 reg mod 1 0 0 mem 1 1 reg reg mod reg mem mod reg mem 1 1 0 0 1 reg mod 0 0 1 mem 1 1 reg reg mod reg mem mod reg mem 1 1 1 1 0 reg mod 1 1 0 mem u u u u u u u u u u u u u u u u u u u u u u u 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 www.datasheet.co.kr datasheet pdf - http://www..net/ 26 m pd70325 test1 not1 reg8,cl mem8,cl reg16,cl mem16,cl reg8,imm3 mem8,imm3 reg16,imm4 mem16,imm4 reg8,cl mem8,cl reg16,cl mem16,cl reg8,imm3 mem8,imm3 reg16,imm4 mem16,imm4 operation code 0 0 0 1 0 0 0 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 group mnemonic operand 3 3 to 5 3 3 to 5 4 4 to 6 4 4 to 6 3 3 to 5 3 3 to 5 4 4 to 6 4 4 to 6 bytes flags ac cy v p s z reg8 bit no. cl = 0: z 1 reg8 bit no. cl = 1: z 0 (mem8) bit no. cl = 0: z 1 (mem8) bit no. cl = 1: z 0 reg16 bit no. cl = 0: z 1 reg16 bit no. cl = 1: z 0 (mem16) bit no. cl = 0: z 1 (mem16) bit no. cl = 1: z 0 reg8 bit no. imm3 = 0: z 1 reg8 bit no. imm3 = 1: z 0 (mem8) bit no. imm3 = 0: z 1 (mem8) bit no. imm3 = 1: z 0 reg16 bit no. imm4 = 0: z 1 reg16 bit no. imm4 = 1: z 0 (mem16) bit no. imm4 = 0: z 1 (mem16) bit no. imm4 = 1: z 0 reg8 bit no. cl reg8 bit no. cl (mem8) bit no. cl (mem8) bit no. cl reg16 bit no. cl reg16 bit no. cl (mem16) bit no. cl (mem16) bit no. cl reg8 bit no. imm3 reg8 bit no. imm3 (mem8) bit no. imm3 (mem8) bit no. imm3 reg16 bit no. imm4 reg16 bit no. imm4 (mem16) bit no. imm4 (mem16) bit no. imm4 operation bit manipu- lation 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem u u u u u u u u 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u u u u u u u u u 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2nd byte note 3rd byte note 1st byte = 0fh cy cy 1 1 1 1 1 0 1 0 1 cy not1 note www.datasheet.co.kr datasheet pdf - http://www..net/ 27 m pd70325 clr1 set1 reg8,cl mem8,cl reg16,cl mem16,cl reg8,imm3 mem8,imm3 reg16,imm4 mem16,imm4 reg8,cl mem8,cl reg16,cl mem16,cl reg8,imm3 mem8,imm3 reg16,imm4 mem16,imm4 operation code 0 0 0 1 0 0 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 group mnemonic operand 3 3 to 5 3 3 to 5 4 4 to 6 4 4 to 6 3 3 to 5 3 3 to 5 4 4 to 6 4 4 to 6 bytes flags ac cy v p s z reg8 bit no. cl 0 (mem8) bit no. cl 0 reg16 bit no. cl 0 (mem16) bit no. cl 0 reg8 bit no. imm3 0 (mem8) bit no. imm3 0 reg16 bit no. imm4 0 (mem16) bit no. imm4 0 reg8 bit no. cl 1 (mem8) bit no. cl 1 reg16 bit no. cl 1 (mem16) bit no. cl 1 reg8 bit no. imm3 1 (mem8) bit no. imm3 1 reg16 bit no. imm4 1 (mem16) bit no. imm4 1 operation bit manipu- lation 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 0 0 1 1 0 1 1 1 0 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2nd byte note 3rd byte note note 1st byte = 0fh 0 1 cy 0 dir 0 cy 1 dir 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 1 cy dir cy dir clr1 set1 www.datasheet.co.kr datasheet pdf - http://www..net/ 28 m pd70325 shl reg,1 mem,1 reg,cl mem,cl reg,imm8 mem,imm8 operation code 1 1 0 1 0 0 0 w 1 1 0 1 0 0 0 w 1 1 0 1 0 0 1 w 1 1 0 1 0 0 1 w 1 1 0 0 0 0 0 w 1 1 0 0 0 0 0 w 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 group mnemonic operand 2 2 to 4 2 2 to 4 3 3 to 5 bytes flags ac cy v p s z cy reg msb, reg reg 2 when reg msb cy, v ? 1 when reg msb = cy, v ? 0 cy ? (mem) msb, (mem) ? (mem) 2 when (mem) msb cy, v ? 1 when (mem) msb = cy, v ? 0 the following operations are repeated while temp ? cl and temp 0. cy ? reg msb, reg ? reg 2 temp ? temp e 1 the following operations are repeated while temp ? cl and temp 0. cy ? (mem) msb, (mem) ? (mem) 2 temp ? temp e 1 the following operations are repeated while temp ? imm8 and temp 0. cy ? reg msb, reg ? reg 2 temp ? temp e 1 the following operations are repeated while temp ? imm8 and temp 0. cy ? (mem) msb, (mem) ? (mem) 2 temp ? temp e 1 operation shift 1 1 1 0 0 reg mod 1 0 0 mem 1 1 1 0 0 reg mod 1 0 0 mem 1 1 1 0 0 reg mod 1 0 0 mem u u u u u u u u u u www.datasheet.co.kr datasheet pdf - http://www..net/ 29 m pd70325 shr shra reg,1 mem,1 reg,cl mem,cl reg,imm8 mem,imm8 reg,1 mem,1 reg,cl mem,cl reg,imm8 mem,imm8 operation code 1 1 0 1 0 0 0 w 1 1 0 1 0 0 0 w 1 1 0 1 0 0 1 w 1 1 0 1 0 0 1 w 1 1 0 0 0 0 0 w 1 1 0 0 0 0 0 w 1 1 0 1 0 0 0 w 1 1 0 1 0 0 0 w 1 1 0 1 0 0 1 w 1 1 0 1 0 0 1 w 1 1 0 0 0 0 0 w 1 1 0 0 0 0 0 w 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 group mnemonic operand 2 2 to 4 2 2 to 4 3 3 to 5 2 2 to 4 2 2 to 4 3 3 to 5 bytes flags ac cy v p s z cy reg lsb, reg reg 2 reg msb bit following reg msb: v ? 1 reg msb = bit following reg msb: v ? 0 cy ? (mem) lsb, (mem) ? (mem) 2 (mem) msb bit following (mem) msb: v ? 1 (mem) msb = bit following (mem) msb: v ? 0 the following operations are repeated while temp ? cl and temp 0. cy ? reg lsb, reg ? reg 2 temp ? temp e 1 the following operations are repeated while temp ? cl and temp 0. cy ? (mem) lsb, (mem) ? (mem) 2 temp ? temp e 1 the following operations are repeated while temp ? imm8 and temp 0. cy ? reg lsb, reg ? reg 2 temp ? temp e 1 the following operations are repeated while temp ? imm8 and temp 0. cy ? (mem) lsb, (mem) ? (mem) 2 temp ? temp e 1 cy ? reg lsb, reg ? reg 2, v ? 0 the operand msb remains the same status. cy ? (mem) lsb, (mem) ? (mem) 2, v ? 0 the operand msb remains the same status. the following operations are repeated while temp ? cl and temp 0. cy ? reg lsb, reg ? reg 2 temp ? temp e 1 the operand msb remains the same status. the following operations are repeated while temp ? cl and temp 0. cy ? (mem) lsb, (mem) ? (mem) 2 the operand msb remains the same status. the following operations are repeated while temp ? imm8 and temp 0. cy ? reg lsb, reg ? reg 2 temp ? temp e 1 the operand msb remains the same status. the following operations are repeated while temp ? imm8 and temp 0. cy ? (mem) lsb, (mem) ? (mem) 2 temp ? temp e 1 the operand msb remains the same status. operation shift 1 1 1 0 1 reg mod 1 0 1 mem 1 1 1 0 1 reg mod 1 0 1 mem 1 1 1 0 1 reg mod 1 0 1 mem 1 1 1 1 1 reg mod 1 1 1 mem 1 1 1 1 1 reg mod 1 1 1 mem 1 1 1 1 1 reg mod 1 1 1 mem u u u u u u u u u u u u u u u u 0 0 u u u u temp ? temp e 1 www.datasheet.co.kr datasheet pdf - http://www..net/ 30 m pd70325 rol ror reg,1 mem,1 reg,cl mem,cl reg,imm8 mem,imm8 reg,1 mem,1 reg,cl mem,cl reg,imm8 mem,imm8 operation code 1 1 0 1 0 0 0 w 1 1 0 1 0 0 0 w 1 1 0 1 0 0 1 w 1 1 0 1 0 0 1 w 1 1 0 0 0 0 0 w 1 1 0 0 0 0 0 w 1 1 0 1 0 0 0 w 1 1 0 1 0 0 0 w 1 1 0 1 0 0 1 w 1 1 0 1 0 0 1 w 1 1 0 0 0 0 0 w 1 1 0 0 0 0 0 w 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 group mnemonic operand 2 2 to 4 2 2 to 4 3 3 to 5 2 2 to 4 2 2 to 4 3 3 to 5 bytes flags ac cy v p s z cy reg msb, reg reg 2 + cy reg msb cy: v 1 reg msb = cy: v 0 cy (mem) msb, (mem) (mem) 2 + cy (mem) msb cy: v 1 (mem) msb = cy: v 0 the following operations are repeated while temp cl and temp 0. cy reg msb, reg reg 2 + cy temp temp C 1 the following operations are repeated while temp cl and temp 0. cy (mem) msb, (mem) (mem) 2 + cy temp temp C 1 the following operations are repeated while temp imm8 and temp 0. cy reg msb, reg reg 2 + cy temp temp C 1 the following operations are repeated while temp imm8 and temp 0. cy (mem) msb, (mem) (mem) 2 + cy temp temp C 1 cy reg lsb, reg reg 2 reg msb cy reg msb bit following reg msb: v 1 reg msb = bit following reg msb: v 0 cy (mem) lsb, (mem) (mem) 2 (mem) msb cy (mem) msb bit following (mem) msb: v 1 (mem) msb = bit following (mem) msb: v 0 the following operations are repeated while temp cl and temp 0. cy reg lsb, reg reg 2 reg msb cy temp temp C 1 the following operations are repeated while temp cl and temp 0. cy (mem) lsb, (mem) (mem) 2 (mem) msb cy temp temp C 1 the following operations are repeated while temp imm8 and temp 0. cy reg lsb, reg reg 2 reg msb cy temp temp C 1 the following operations are repeated while temp imm8 and temp 0. cy (mem) lsb, (mem) (mem) 2 (mem) msb cy temp temp C 1 operation rotate 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 1 reg mod 0 0 1 mem 1 1 0 0 1 reg mod 0 0 1 mem 1 1 0 0 1 reg mod 0 0 1 mem u u u u u u u u www.datasheet.co.kr datasheet pdf - http://www..net/ 31 m pd70325 rolc reg,1 mem,1 reg,cl mem,cl reg,imm8 mem,imm8 operation code 1 1 0 1 0 0 0 w 1 1 0 1 0 0 0 w 1 1 0 1 0 0 1 w 1 1 0 1 0 0 1 w 1 1 0 0 0 0 0 w 1 1 0 0 0 0 0 w 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 group mnemonic operand 2 2 to 4 2 2 to 4 3 3 to 5 bytes flags ac cy v p s z tmpcy cy, cy reg msb reg reg 2 + tmpcy reg msb cy: v ? 1 reg msb = cy: v ? 0 tmpcy ? cy, cy ? (mem) msb (mem) ? (mem) 2 + tmpcy (mem) msb cy: v ? 1 (mem) msb = cy: v ? 0 the following operations are repeated while temp ? cl and temp 0. tmpcy ? cy, cy ? reg msb reg ? reg 2 + tmpcy temp ? temp e 1 the following operations are repeated while temp ? cl and temp 0. tmpcy ? cy, cy ? (mem) msb (mem) ? (mem) 2 + tmpcy temp ? temp e 1 the following operations are repeated while temp ? imm8 and temp 0. tmpcy ? cy, cy ? reg msb reg ? reg 2 + tmpcy temp ? temp e 1 the following operations are repeated while temp ? imm8 and temp 0. tmpcy ? cy, cy ? (mem) msb (mem) ? (mem) 2 + tmpcy temp ? temp e 1 operation rotate 1 1 0 1 0 reg mod 0 1 0 mem 1 1 0 1 0 reg mod 0 1 0 mem 1 1 0 1 0 reg mod 0 1 0 mem u u u u www.datasheet.co.kr datasheet pdf - http://www..net/ 32 m pd70325 rorc reg,1 mem,1 reg,cl mem,cl reg,imm8 mem,imm8 operation code 1 1 0 1 0 0 0 w 1 1 0 1 0 0 0 w 1 1 0 1 0 0 1 w 1 1 0 1 0 0 1 w 1 1 0 0 0 0 0 w 1 1 0 0 0 0 0 w 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 group mnemonic operand 2 2 to 4 2 2 to 4 3 3 to 5 bytes flags ac cy v p s z tmpcy cy, cy reg lsb reg reg 2 reg msb ? tmpcy reg msb bit following reg msb: v ? 1 reg msb = bit following reg msb: v ? 0 tmpcy ? cy, cy ? (mem) lsb (mem) ? (mem) 2 (mem) msb ? tmpcy (mem) msb bit following (mem) msb: v ? 1 (mem) msb = bit following (mem) msb: v ? 0 the following operations are repeated while temp ? cl and temp 0. tmpcy ? cy, cy ? reg lsb reg ? reg 2 reg msb ? tmpcy temp ? temp e 1 the following operations are repeated while temp ? cl and temp 0. tmpcy ? cy, cy ? (mem) lsb (mem) ? (mem) 2 (mem) msb ? tmpcy temp ? temp e 1 the following operations are repeated while temp ? imm8 and temp 0. tmpcy ? cy, cy ? reg lsb reg ? reg 2 reg msb ? tmpcy temp ? temp e 1 the following operations are repeated while temp ? imm8 and temp 0. tmpcy ? cy, cy ? (mem) lsb (mem) ? (mem) 2 (mem) msb ? tmpcy temp ? temp e 1 operation rotate 1 1 0 1 1 reg mod 0 1 1 mem 1 1 0 1 1 reg mod 0 1 1 mem 1 1 0 1 1 reg mod 0 1 1 mem u u u u www.datasheet.co.kr datasheet pdf - http://www..net/ 33 m pd70325 call ret near-proc regptr16 memptr16 far-proc memptr32 pop-value pop-value operation code 1 1 1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 1 1 0 0 1 0 1 1 1 1 0 0 1 0 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 group mnemonic operand 3 2 2 to 4 5 2 to 4 1 3 1 3 bytes flags ac cy v p s z (sp C 1, sp C 2) pc, sp sp C 2 pc pc + disp (sp C 1, sp C 2) pc, pc regptr16 sp sp C 2 (sp C 1, sp C 2) pc, sp sp C 2 pc (memptr16) (sp C 1, sp C 2) ps, (sp C 3, sp C 4) pc sp sp C 4 ps seg, pc offset (sp C 1, sp C 2) ps, (sp C 3, sp C 4) pc sp sp C 4 ps (memptr32 + 2), pc (memptr32) pc (sp + 1, sp) sp sp + 2 pc (sp + 1, sp) sp sp + 2, sp sp + pop-value pc (sp + 1, sp) ps (sp + 3, sp + 2) sp sp + 4 pc (sp + 1, sp) ps (sp + 3, sp + 2) sp sp + 4, sp sp + pop-value operation sub- routine control 1 1 0 1 0 reg mod 0 1 0 mem mod 0 1 1 mem www.datasheet.co.kr datasheet pdf - http://www..net/ 34 m pd70325 push pop prepare dispose br mem16 reg16 sreg psw r imm8 imm16 mem16 reg16 sreg psw r imm16,imm8 near-label short-label regptr16 memptr16 far-label memptr32 operation code 1 1 1 1 1 1 1 1 0 1 0 1 0 reg 0 0 0 sreg 1 1 0 1 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 1 1 1 0 1 0 1 1 reg 0 0 0 sreg 1 1 1 1 0 0 1 1 1 0 1 0 1 1 0 0 0 0 1 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 group mnemonic operand 2 to 4 1 1 1 1 2 3 2 to 4 1 1 1 1 4 1 3 2 2 2 to 4 5 2 to 4 bytes flags ac cy v p s z (sp C 1, sp C 2) (mem16) sp sp C 2 (sp C 1, sp C 2) reg16 sp sp C 2 (sp C 1, sp C 2) sreg sp sp C 2 (sp C 1, sp C 2) psw sp sp C 2 push registers on the stack (sp C 1, sp C 2) imm8 sign extension sp sp C 2 (sp C 1, sp C 2) imm16 sp sp C 2 (mem16) (sp + 1, sp) sp sp + 2 reg16 (sp + 1, sp) sp sp + 2 sreg (sp + 1, sp) sreg: ss, ds0, ds1 sp sp + 2 psw (sp + 1, sp) sp sp + 2 pop registers from the stack prepare new stack frame dispose of stack frame pc pc + disp pc pc + ext-disp8 pc regptr16 pc (memptr16) ps seg pc offset ps (memptr32 + 2) pc (memptr32) operation stack manipu- lation mod 1 1 0 mem mod 0 0 0 mem 1 1 1 0 0 reg mod 1 0 0 mem mod 1 0 1 mem branch rrrrrr www.datasheet.co.kr datasheet pdf - http://www..net/ 35 m pd70325 bv bnv bc bl bnc bnl be bz bne bnz bnh bh bn bp bpe bpo blt bge ble bgt dbnzne dbnze dbnz bcwz btclr note short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label sfr, imm3, short-label operation code 0 1 1 1 0 0 0 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 group mnemonic operand 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 5 bytes flags ac cy v p s z if v = 1 if v = 0 if cy = 1 if cy = 0 if z = 1 if z = 0 if cy M z = 1 if cy M z = 0 if s = 1 if s = 0 if p = 1 if p = 0 if s M v = 1 if s M v = 0 if (s M v) M z = 1 if (s M v) M z = 0 cw = cw C 1 if z = 0 and cw 0 cw = cw C 1 if z = 1 and cw 0 cw = cw C 1 if cw 0 if cw = 0 when (sfr) bit no. imm3 = 1, pc pc + ext-disp8 and (sfr) bit no. imm3 0. operation condi- tional branch 1 0 0 1 1 1 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 0 0 1 1 1 1 pc pc + ext-disp8 pc pc + ext-disp8 pc pc + ext-disp8 pc pc + ext-disp8 pc pc + ext-disp8 pc pc + ext-disp8 pc pc + ext-disp8 pc pc + ext-disp8 pc pc + ext-disp8 pc pc + ext-disp8 pc pc + ext-disp8 pc pc + ext-disp8 pc pc + ext-disp8 pc pc + ext-disp8 pc pc + ext-disp8 pc pc + ext-disp8 pc pc + ext-disp8 pc pc + ext-disp8 pc pc + ext-disp8 pc pc + ext-disp8 note this instruction is newly added to the pd70108/70116. m www.datasheet.co.kr datasheet pdf - http://www..net/ 36 m pd70325 brk brkv reti retrbi note fint note chkind brkcs note tsksw note 3 imm8 ( 3) reg16,mem32 reg16 reg16 operation code 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 1 0 0 1 1 1 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 reg 0 0 0 0 1 1 1 1 1 1 1 1 1 reg 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 group mnemonic operand 1 2 1 1 2 2 2 to 4 3 3 bytes flags ac cy v p s z (sp C 1, sp C 2) psw, (sp C 3, sp C 4) ps, (sp C 5, sp C 6) pc, sp sp C 6 ie 0, brk 0 ps (15, 14), pc (13, 12) (sp C 1, sp C 2) psw, (sp C 3, sp C 4) ps, (sp C 5, sp C 6) pc, sp sp C 6 ie 0, brk 0 ps (n 4 + 3, n 4 + 2), pc (n 4 + 1, n 4) n = imm8 when v = 1, (sp C 1, sp C 2) psw, (sp C 3, sp C 4) ps, (sp C 5, sp C 6) pc, sp sp C 6 ie 0, brk 0 ps (19, 18), pc (17, 16) pc (sp + 1, sp), ps (sp + 3, sp + 2), psw (sp + 5, sp + 4), sp sp + 6 pc save pc, psw save psw reports the cpu internal interrupt controller that interrupt service routine operation has ended. when (mem32) > reg16 or (mem32 + 2) < reg16, (sp C 1, sp C 2) psw, (sp C 3, sp C 4) ps, (sp C 5, sp C 6) pc, sp sp C 6 ie 0, brk 0 ps (23, 22), pc (21, 20) rb2 C 0 lower 3 bits of reg16, ie 0, brk 0 save psw psw, save pc pc, pc vector pc rb2 ?0 lower 3 bits of reg16, old register bank save psw and save pc psw and pc, psw and pc new register bank save psw and save pc operation interrupt 1 0 0 1 0 0 0 1 1 0 0 1 0 0 1 0 mod reg mem 0 0 1 0 1 1 0 1 1 0 0 1 0 1 0 0 note these instructions are newly added to the pd70108/70116. m register bank switch r r r r r r r r r r r r www.datasheet.co.kr datasheet pdf - http://www..net/ 37 m pd70325 halt stop note 2 poll di ei buslock fpo1 note 3 fpo2 note 3 nop note 1 fp-op fp-op,mem fp-op fp-op,mem operation code 1 1 1 1 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 0 1 1 x x x 1 1 0 1 1 x x x 0 1 1 0 0 1 1 x 0 1 1 0 0 1 1 x 1 0 0 1 0 0 0 0 0 0 1 sreg 1 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 group mnemonic operand 1 2 1 1 1 1 2 2 to 4 2 2 to 4 1 1 bytes flags ac cy v p s z cpu halt cpu stop poll and wait ie 0 ie 1 bus lock prefix no operation data bus (mem) no operation data bus (mem) no operation segment override prefix operation cpu control 1 0 0 1 1 1 1 0 1 1 y y y z z z mod y y y mem 1 1 y y y z z z mod y y y mem notes 1. ds0:, ds1:, ps: and ss: 2. this instruction is newly added to the pd70108/70116. 3. in the pd70320, an interrupt is generated without executing these instructions. m m www.datasheet.co.kr datasheet pdf - http://www..net/ 38 m pd70325 mod mem 00 clocks 01 clocks 10 clocks 000 bw + ix 3 bw + ix + disp8 3 bw + ix + disp16 4 001 bw + iy 3 bw + iy + disp8 3 bw + iy + disp16 4 010 bp + ix 3 bp + ix + disp8 3 bp + ix + disp16 4 011 bp + iy 3 bp + iy + disp8 3 bp + iy + disp16 4 100 ix 3 ix + disp8 3 ix + disp16 4 101 iy 3 iy + disp8 3 iy + disp16 4 110 direct address 3 bp + disp8 3 bp + disp16 4 111 bw 3 bw + disp8 3 bw + disp16 4 2.4 number of clocks table (1) legend the number of clocks, for memory operand, differs among addressing modes. so, use the following values for ea items shown in table 2-9 number of clocks . table 2-8. number of clocks for each memory addressing t indicates the number of wait states. use any number of waits starting at 0 (no wait). www.datasheet.co.kr datasheet pdf - http://www..net/ 39 m pd70325 number of clocks byte processing word processing group mnemonic operands on-chip ram on-chip ram on-chip ram on-chip ram access enable access disable access enable access disable data mov reg, reg 2 2 2 2 transfer mem, reg ea + 4 + t ea + 2 ea + 6 + 2t ea + 2 reg, mem ea + 6 + t ea + 6 + t ea + 8 + 2t ea + 8 + 2t mem, imm ea + 5 + t ea + 5 + t ea + 5 + 2t ea + 5 + t reg, imm 5 5 6 6 acc, dmem 9 + t 9 + t 11 + 2t 11 + 2t dmem, acc 7 + t 5 9 + 2t 5 sreg, reg16 4 4 sreg, mem16 ea + 10 + 2t ea + 10 + 2t reg16, sreg 3 3 mem16, sreg ea + 7 + 2t ea + 3 ds0, reg16, ea + 19 + 4t ea + 19 + 4t mem32 ds1, reg16, ea + 19 + 4t ea + 19 + 4t mem32 ah, psw 2 2 psw, ah 3 3 ldea reg16, mem16 ea + 2 ea + 2 trans src-table 10 + t 10 + t xch reg, reg 3 3 3 3 mem, reg/ ea + 10 + 2t ea + 8 + 2t ea + 14 + 2t ea + 10 + 2t reg, mem aw, reg16/ 4 4 reg16, aw movspa 16 16 movspb reg16 11 11 repeat repc 2 2 2 2 prefix repnc 2 2 2 2 rep/repe/ 2 2 2 2 repz repne/ 2 2 2 2 repnz primitive movkb note 1 dst-block, 20 + 2t 16 + t 24 + 4t 20 + 2t block note 2 src-block 16 + (16 + 2t)n 16 + (12 + t)n 16 + (20 + 4t)n 16 + (12 + 2t)n transfer cmpkb note 1 dst-block, 23 + 2t 19 + t 27 + 4t 21 + 4t note 2 src-block 16 + (21 + 2t)n 16 + (21 + 2t)n 16 + (25 + 4t)n 16 + (25 + 2t)n notes 1. not repeated 2. repeated, n: number of transfer times (n 1) (2) number of clocks table 2-9. number of clocks (1/10) www.datasheet.co.kr datasheet pdf - http://www..net/ 40 m pd70325 table 2-9. number of clocks (2/10) notes 1. not repeated 2. repeated, n: number of transfer times (n 1) 3. when ibrk = 1 number of clocks byte processing word processing group mnemonic operands on-chip ram on-chip ram on-chip ram on-chip ram access enable access disable access enable access disable primitive cmpm note 1 dst-block 17 + t 17 + t 19 + 2t 19 + 2t block note 2 src-block 16 + (15 + t)n 16 + (15 + t)n 16 + (17 + 2t)n 16 + (17 + 2t)n transfer ldm note 1 src-block 12 + t 12 + t 14 + 2t 14 + 2t note 2 16 + (10 + t)n 16 + (10 + t)n 16 + (12 + 2t)n 16 + (12 + 2t)n stm note 1 dst-block 12 + t 10 14 + 2t 10 note 2 16 + (8 + t)n 16 + (6 + t)n 16 + (10 + 2t)n 16 + (6 + 2t)n bit field ins reg8, reg8 63 to 155 (the processing differs among bit lengths.) manipula- reg8, imm4 64 to 156 (the processing differs among bit lengths.) tion ext reg8, reg8 41 to 121 (the processing differs among bit lengths.) reg8, imm4 42 to 122 (the processing differs among bit lengths.) i/o in acc, imm8 14 + t 14 + t 16 + 2t 16 + 2t note 3 acc, dw 13 + t 13 + t 15 + 2t 15 + 2t out imm8, acc 10 + t 10 + t 10 + 2t 10 + 2t note 3 dw, acc 9 + t 9 + t 9 + 2t 9 + 2t primitive inm dst-block, dw 19 + 2t 17 + 2t 21 + 4t 17 + 4t i/o note 3 18 + (13 + 2t)n 18 + (11 + 2t)n 18 + (15 + 4t)n 18 + (11 + 4t)n outm dw, src-block 19 + 2t 17 + 2t 21 + 4t 17 + 4t note 3 18 + (13 + 2t)n 18 + (11 + 2t)n 18 + (15 + 4t)n 18 + (11 + 4t)n addition/ add reg, reg 2 2 2 2 subtraction mem, reg ea + 8 + 2t ea + 6 + t ea + 12 + 4t ea + 8 + 2t reg, mem ea + 6 + t ea + 6 + t ea + 8 + 2t ea + 8 + 2t reg, imm 5 5 6 6 mem, imm ea + 9 + 2t ea + 7 + 2t ea + 14 + 4t ea + 10 + 4t acc, imm 5 5 6 6 addc reg, reg 2 2 2 2 mem, reg ea + 8 + 2t ea + 6 + t ea + 12 + 4t ea + 8 + 2t reg, mem ea + 6 + t ea + 6 + t ea + 8 + 2t ea + 8 + 2t reg, imm 5 5 6 6 mem, imm ea + 9 + 2t ea + 7 + 2t ea + 14 + 4t ea + 10 + 4t acc, imm 5 5 6 6 www.datasheet.co.kr datasheet pdf - http://www..net/ 41 m pd70325 table 2-9. number of clocks (3/10) note n: 1/2 of the number of bcd digits number of clocks byte processing word processing group mnemonic operands on-chip ram on-chip ram on-chip ram on-chip ram access enable access disable access enable access disable addition/ sub reg, reg 2 2 2 2 subtraction mem, reg ea + 8 + 2t ea + 6 + t ea + 12 + 4t ea + 8 + 2t reg, mem ea + 6 + t ea + 6 + t ea + 8 + 2t ea + 8 + 2t reg, imm 5 5 6 6 mem, imm ea + 9 + 2t ea + 7 + 2t ea + 14 + 4t ea + 10 + 4t acc, imm 5 5 6 6 subc reg, reg 2 2 2 2 mem, reg ea + 8 + 2t ea + 6 + t ea + 12 + 4t ea + 8 + 2t reg, mem ea + 6 + t ea + 6 + t ea + 8 + 2t ea + 8 + 2t reg, imm 5 5 6 6 mem, imm ea + 9 + 2t ea + 7 + 2t ea + 14 + 4t ea + 10 + 4t acc, imm 5 5 6 6 bcd add4s note 22 + (27 + 3t)n 22 + (25 + 3t)n operation sub4s note 22 + (27 + 3t)n 22 + (25 + 3t)n cmp4s note 22 + (23 + 3t)n 22 + (23 + 3t)n rol4 reg8 17 17 mem8 ea + 18 + 2t ea + 16 + 2t ror4 reg8 21 21 mem8 ea + 24 + 2t ea + 22 + 2t increment / inc reg8 5 5 decrement mem8 ea + 11 + 2t ea + 9 + 2t ea + 15 + 4t ea + 11 + 4t reg16 2 2 dec reg8 5 5 mem8 ea + 11 + 2t ea + 9 + 2t ea + 15 + 4t ea + 11 + 4t reg16 2 2 multiplica- mulu reg8 24 24 tion mem8 ea + 26 + t ea + 26 + t reg16 32 32 mem16 ea + 34 + 2t ea + 34 + 2t www.datasheet.co.kr datasheet pdf - http://www..net/ 42 m pd70325 table 2-9. number of clocks (4/10) number of clocks byte processing word processing group mnemonic operands on-chip ram on-chip ram on-chip ram on-chip ram access enable access disable access enable access disable multiplica- mul reg8 31 to 40 31 to 40 tion mem8 ea + 33 + t to ea + 33 + t to ea + 42 + t ea + 42 + t reg16 39 to 48 39 to 48 mem16 ea + 43 + 2t to ea + 43 + 2t to ea + 52 + 2t ea + 52 + 2t reg16, (reg16,) 39 to 49 39 to 49 imm8 reg16, mem16, ea + 43 + 2t to ea + 43 + 2t to imm8 ea + 53 + 2t ea + 53 + 2t reg16, (reg16,) 40 to 50 40 to 50 imm16 reg16, mem16, ea + 44 + 2t to ea + 44 + 2t to imm16 ea + 54 + 2t ea + 54 + 2t unsigned divu reg8 31 31 division mem8 ea + 33 + t ea + 33 + t reg16 39 39 mem16 ea + 43 + 2t ea + 43 + 2t signed div reg8 46 to 56 46 to 56 division mem8 ea + 48 + t to ea + 48 + t to ea + 58 + t ea + 58 + t reg16 54 to 64 54 to 64 mem16 ea + 58 + 2t to ea + 58 + 2t to ea + 68 + 2t ea + 68 + 2t bcd adjba 17 17 adjustment adj4a 9 9 adjbs 17 17 adj4s 9 9 data cvtbd 19 19 conversion cvtdb 20 20 cvtbw 3 3 cvtwl 8 8 compare cmp reg, reg 2 2 2 2 mem, reg ea + 6 + t ea + 6 + t ea + 8 + 2t ea + 8 + 2t reg, mem ea + 6 + t ea + 6 + t ea + 8 + 2t ea + 8 + 2t reg, imm 5 5 6 6 mem, imm ea + 7 + t ea + 7 + t ea + 10 + 2t ea + 10 + 2t acc, imm 5 5 6 6 www.datasheet.co.kr datasheet pdf - http://www..net/ 43 m pd70325 table 2-9. number of clocks (5/10) number of clocks byte processing word processing group mnemonic operands on-chip ram on-chip ram on-chip ram on-chip ram access enable access disable access enable access disable comple not reg 5 5 5 5 ment mem ea + 11 + 2t ea + 9 + t ea + 15 + 4t ea + 11 + 2t operation neg reg 5 5 5 5 mem ea + 11 + 2t ea + 9 + t ea + 15 + 4t ea + 11 + 2t logical test reg, reg 4 4 4 4 operation mem, reg/ ea + 8 + t ea + 8 + t ea + 10 + 2t ea + 10 + 2t reg, mem reg, imm 7 7 8 8 mem, imm ea + 11 + t ea + 11 + t ea + 11 + 2t ea + 11 + 2t acc, imm 5 5 6 6 and reg, reg 2 2 2 2 mem, reg ea + 8 + 2t ea + 6 + t ea + 12 + 4t ea + 8 + 2t reg, mem ea + 6 + t ea + 6 + t ea + 8 + 2t ea + 8 + 2t reg, imm 5 5 6 6 mem, imm ea + 9 + t ea + 7 + t ea + 14 + 4t ea + 10 + 4t acc, imm 5 5 6 6 or reg, reg 2 2 2 2 mem, reg ea + 8 + 2t ea + 6 + t ea + 12 + 4t ea + 8 + 2t reg, mem ea + 6 + t ea + 6 + t ea + 8 + 2t ea + 8 + 2t reg, imm 5 5 6 6 mem, imm ea + 9 + t ea + 7 + t ea + 14 + 4t ea + 10 + 4t acc, imm 5 5 6 6 xor reg, reg 2 2 2 2 mem, reg ea + 8 + 2t ea + 6 + t ea + 12 + 4t ea + 8 + 2t reg, mem ea + 6 + t ea + 6 + t ea + 8 + 2t ea + 8 + 2t reg, imm 5 5 6 6 mem, imm ea + 9 + t ea + 7 + t ea + 14 + 4t ea + 10 + 4t acc, imm 5 5 6 6 bit test1 reg8, cl 7 7 manipula- mem8, cl ea + 11 + t ea + 11 + t tion reg16, cl 7 7 mem16, cl ea + 13 + 2t ea + 13 + 2t reg8, imm3 6 6 mem8, imm3 ea + 8 + t ea + 8 + t reg16, imm4 6 6 mem16, imm4 ea + 10 + 2t ea + 10 + 2t not1 reg8, cl 7 7 mem8, cl ea + 13 + 2t ea + 11 + t reg16, cl 7 7 www.datasheet.co.kr datasheet pdf - http://www..net/ 44 m pd70325 table 2-9. number of clocks (6/10) note n: shift count number of clocks byte processing word processing group mnemonic operands on-chip ram on-chip ram on-chip ram on-chip ram access enable access disable access enable access disable bit not1 mem16, cl ea + 17 + 4t ea + 13 + 2t manipula- reg8, imm3 6 6 tion mem8, imm3 ea + 10 + 2t ea + 8 + t reg16, imm4 6 6 mem16, imm4 ea + 14 + 4t ea + 10 + 2t not1 cy 2 2 2 2 bit clr1 reg8, cl 8 8 manipula- mem8, cl ea + 14 + 2t ea + 12 + t tion reg16, cl 8 8 mem16, cl ea + 18 + 4t ea + 14 + 2t reg8, imm3 7 7 mem8, imm3 ea + 11 + 2t ea + 9 + t reg16, imm4 7 7 mem16, imm4 ea + 15 + 4t ea + 10 + 2t set1 reg8, cl 7 7 mem8, cl ea + 13 + 2t ea + 11 + t reg16, cl 7 7 mem16, cl ea + 17 + 4t ea + 13 + 2t reg8, imm3 6 6 mem8, imm3 ea + 10 + 2t ea + 8 + t reg16, imm4 6 6 mem16, imm4 ea + 14 + 4t ea + 10 + 2t clr1 cy 2 2 2 2 dir 2 2 2 2 set1 cy 2 2 2 2 dir 2 2 2 2 shift shl reg,1 8 8 8 8 mem, 1 ea + 14 + 2t ea + 12 + t ea + 18 + 4t ea + 14 + 2t reg, cl 11 + 2n 11 + 2n 11 + 2n 11 + 2n mem, cl ea + 17 + 2t + 2n ea + 15 + t + 2n ea + 21 + 4t + 2n ea + 17 + 2t + 2n reg, imm8 9 + 2n 9 + 2n 9 + 2n 9 + 2n mem, imm8 ea + 13 + 2t + 2n ea + 11 + t + 2n ea + 17 + 4t + 2n ea + 13 + 2t + 2n shr reg, 1 8 8 8 8 mem, 1 ea + 14 + 2t ea + 12 + t ea + 18 + 4t ea + 14 + 2t note www.datasheet.co.kr datasheet pdf - http://www..net/ 45 m pd70325 table 2-9. number of clocks (7/10) note n: shift count number of clocks byte processing word processing group mnemonic operands on-chip ram on-chip ram on-chip ram on-chip ram access enable access disable access enable access disable shift shr reg, cl 11 + 2n 11 + 2n 11 + 2n 11 + 2n mem, cl ea + 17 + 2t + 2n ea + 15 + t + 2n ea + 21 + 4t + 2n ea + 17 + 2t + 2n reg, imm8 9 + 2n 9 + 2n 9 + 2n 9 + 2n mem, imm8 ea + 13 + 2t + 2n ea + 11 + t + 2n ea + 17 + 4t + 2n ea + 13 + 2t + 2n shra reg,1 8 8 8 8 mem, 1 ea + 14 + 2t ea + 12 + t ea + 18 + 4t ea + 14 + 2t reg, cl 11 + 2n 11 + 2n 11 + 2n 11 + 2n mem, cl ea + 17 + 2t + 2n ea + 15 + t + 2n ea + 21 + 4t + 2n ea + 17 + 2t + 2n reg, imm8 9 + 2n 9 + 2n 9 + 2n 9 + 2n mem, imm8 ea + 13 + 2t + 2n ea + 11 + t + 2n ea + 17 + 4t + 2n ea + 13 + 2t + 2n rotate rol reg,1 8 8 8 8 mem, 1 ea + 14 + 2t ea + 12 + t ea + 18 + 4t ea + 14 + 2t reg, cl 11 + 2n 11 + 2n 11 + 2n 11 + 2n mem, cl ea + 17 + 2t + 2n ea + 15 + t + 2n ea + 21 + 4t + 2n ea + 17 + 2t + 2n reg, imm8 9 + 2n 9 + 2n 9 + 2n 9 + 2n mem, imm8 ea + 13 + 2t + 2n ea + 11 + t + 2n ea + 17 + 4t + 2n ea + 13 + 2t + 2n ror reg,1 8 8 8 8 mem, 1 ea + 14 + 2t ea + 12 + t ea + 18 + 4t ea + 14 + 2t reg, cl 11 + 2n 11 + 2n 11 + 2n 11 + 2n mem, cl ea + 17 + 2t + 2n ea + 15 + t + 2n ea + 21 + 4t + 2n ea + 17 + 2t + 2n reg, imm8 9 + 2n 9 + 2n 9 + 2n 9 + 2n mem, imm8 ea + 13 + 2t + 2n ea + 11 + t + 2n ea + 17 + 4t + 2n ea + 13 + 2t + 2n rolc reg,1 8 8 8 8 mem, 1 ea + 14 + 2t ea + 12 + t ea + 18 + 4t ea + 14 + 2t reg, cl 11 + 2n 11 + 2n 11 + 2n 11 + 2n mem, cl ea + 17 + 2t + 2n ea + 15 + t + 2n ea + 21 + 4t + 2n ea + 17 + 2t + 2n reg, imm8 9 + 2n 9 + 2n 9 + 2n 9 + 2n mem, imm8 ea + 13 + 2t + 2n ea + 11 + t + 2n ea + 17 + 4t + 2n ea + 13 + 2t + 2n rorc reg,1 8 8 8 8 mem, 1 ea + 14 + 2t ea + 12 + t ea + 18 + 4t ea + 14 + 2t note note note note note www.datasheet.co.kr datasheet pdf - http://www..net/ 46 m pd70325 number of clocks byte processing word processing group mnemonic operands on-chip ram on-chip ram on-chip ram on-chip ram access enable access disable access enable access disable rotate rorc reg, cl 11 + 2n 11 + 2n 11 + 2n 11 + 2n mem, cl ea + 17 + 2t + 2n ea + 15 + t + 2n ea + 21 + 4t + 2n ea + 17 + 2t + 2n reg, imm8 9 + 2n 9 + 2n 9 + 2n 9 + 2n mem, imm8 ea + 13 + 2t + 2n ea + 11 + t + 2n ea + 17 + 4t + 2n ea + 13 + 2t + 2n subroutine call near-proc 22 + 2t 18 + 2t control regptr16 22 + 2t 18 + 2t memptr16 ea + 26 + 4t ea + 24 + 4t far-proc 38 + 4t 34 + 4t memptr32 ea + 36 + 8t ea + 24 + 8t ret 20 + 2t 20 + 2t pop-value 20 + 2t 20 + 2t 29 + 4t 29 + 4t pop-value 30 + 4t 30 + 4t stack push mem16 ea + 18 + 4t ea + 14 + 4t manipula- reg16 10 + 2t 6 tion sreg 11 + 2t 7 psw 10 + 2t 6 r 82 + 16t 50 imm8 13 + 2t 9 imm16 14 + 2t 10 pop mem16 ea + 16 + 4t ea + 12 + 2t reg16 12 + 2t 12 + 2t sreg 13 + 2t 13 + 2t psw 14 + 2t 14 + 2t r 82 + 16t 58 prepare imm16, imm8 when imm8 = 0, 27 + 2t when imm8 = 1, 39 + 4t when imm8 = n, n > 1, 46 + 19(n C 1) + 4t dispose 12 + 2t 12 + 2t table 2-9. number of clocks (8/10) notes 1. n: shift count 2. depth of procedure block (lexical level) note 1 note 2 www.datasheet.co.kr datasheet pdf - http://www..net/ 47 m pd70325 table 2-9. number of clocks (9/10) number of clocks byte processing word processing group mnemonic operands on-chip ram on-chip ram on-chip ram on-chip ram access enable access disable access enable access disable branch br near-label 12 12 short-label 12 12 regptr16 13 13 memptr16 ea + 17 + 2t ea + 17 + 2t far-label 15 15 memptr32 ea + 25 + 4t ea + 25 + 4t conditional bv short-label 15/8 15/8 branch note bnv short-label 15/8 15/8 bc/bl short-label 15/8 15/8 bnc/bnl short-label 15/8 15/8 be/bz short-label 15/8 15/8 bne/bnz short-label 15/8 15/8 bnh short-label 15/8 15/8 bh short-label 15/8 15/8 bn short-label 15/8 15/8 bp short-label 15/8 15/8 bpe short-label 15/8 15/8 bpo short-label 15/8 15/8 blt short-label 15/8 15/8 bge short-label 15/8 15/8 ble short-label 15/8 15/8 bgt short-label 15/8 15/8 dbnzne short-label 17/8 17/8 dbnze short-label 17/8 17/8 dbnz short-label 17/8 17/8 bcwz short-label 15/8 15/8 btclr sfr, imm3, 29/21 29/21 short-label interrupt brk 3 55 + 10t 43 + 10t imm8 ( 3) 56 + 10t 44 + 10t brkv 55 + 10t 43 + 10t reti 45 + 6t 37 + 2t retrbi 12 12 fint 2 2 2 2 chkind reg16, mem32 ea + 26 + 4t ea + 26 + 4t note in the number of clocks, the value on the left side of / indicates the number of clocks when the condition is true, and the value on the right side indicates the number of clocks when the condition is false. www.datasheet.co.kr datasheet pdf - http://www..net/ 48 m pd70325 table 2-9. number of clocks (10/10) number of clocks byte processing word processing group mnemonic operands on-chip ram on-chip ram on-chip ram on-chip ram access enable access disable access enable access disable register brkcs reg16 15 15 bank switch tsksw reg16 20 20 cpu halt control stop poll di 4444 ei 12 12 12 12 buslock 2 2 2 2 fpo1 fp-op 60 + 10t 48 + 10t fp-op, mem 60 + 10t 48 + 10t fpo2 fp-op 60 + 10t 48 + 10t fp-op, mem 60 + 10t 48 + 10t nop 4 4 4 4 segment override prefix 2 2 2 2 (ds0:, ds1:, ps: and ss:) www.datasheet.co.kr datasheet pdf - http://www..net/ 49 m pd70325 3. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol test conditions rating unit supply voltage v dd C 0.5 to +7.0 v v th C 0.5 to v dd + 0.5 v input voltage v i C 0.5 to v dd + 0.5 v output voltage v o C 0.5 to v dd + 0.5 v output current low i ol each output pin 4.0 ma total 50 ma output current high i oh each output pin C2.0 ma total C20 ma operating ambient temperature t a C10 to +70 c storage temperature t stg C 65 to +150 c cautions 1. do not make direct connections of the output (or input/output) pins of the ic product with each other, and also avoid direct connections to v dd , v cc or gnd. however, the open drain pins or the open collector pins can be directly connected with each other. for the external circuit designed with the timing specifications so that any collision of the outputs from the pins subject to high-impedance state may be prevented, direct connection can be also made. 2. product quality may suffer if the absolute maximum ratings are exceeded for even a single parameter, or even momentarily. in other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. the normal operation and reliability of the product can be only assured with the specifications and the conditions indicated as the dc and ac characteristics. www.datasheet.co.kr datasheet pdf - http://www..net/ 50 m pd70325 oscillator characteristics m pd70325-8 (t a = C10 to +70 c, v dd = +5.0 v 10%, v ss = 0 v, 0 v v th v dd + 0.1 v) m pd70325-10 (t a = C10 to +70 c, v dd = +5.0 v 5%, v ss = 0 v, 0 v v th v dd + 0.1 v) resonator recommended circuit parameter m pd70325-8 m pd70325-10 unit min. max. min. max. ceramic or crystal oscillation 4 16 4 20 mhz resonator frequency (f xx ) external clock x1 input 4 16 4 20 mhz frequency (f x ) x1 input rise/ 0 20 0 15 ns fall time (t xr , t xf ) x1 input high-/ 20 16 ns low-level width (t wxh , t wxl ) cautions 1. mount the oscillation circuit as close to pins x1 and x2 as possible. 2. do not route other signal lines through the area within the dotted line. recommended oscillator constant (1) the following ceramic resonator and external capacity are recommended. (2) the following crystal resonator and external capacity are recommended. remark for more details on the characteristics of the resonators, please contact the manufacturer. hcmos inverter x1 x2 1 2 x1 x2 hcmos inverter open or manufacturer part number recommended constants c1 [pf] c2 [pf] murata mfg. co., ltd. csa16.00mx040 30 30 csa20.00mx040 10 10 tdk fcr16.0m2g 30 30 manufacturer part number recommended constants c1 [pf] c2 [pf] kinseki co., ltd. hc-49/u(kr-100) 22 22 hc-49/u(kr-160) 22 22 hc-49/u(kr-200) 22 22 x1 x2 c1 c2 www.datasheet.co.kr datasheet pdf - http://www..net/ 51 m pd70325 capacitance (t a = 25 c, v dd = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance c i f c = 1 mhz 10 pf output capacitance c o unmeasured pins returned to 0 v. 20 pf input/output capacitance c io 20 pf dc characteristics m pd70325-8 (t a = C10 to +70 c, v dd = +5.0 v 10%) m pd70325-10 (t a = C10 to +70 c, v dd = +5.0 v 5%) ac characteristics (1) m pd70325-8 (t a = C10 to +70 c, v dd = +5.0 v 10%) parameter symbol test conditions min. typ. max. unit input voltage low v il 0 0.8 v input voltage high v ih1 except reset, p10/nmi, x1, x2 2.2 v dd v v ih2 reset, p10/nmi, x1, x2 0.8v dd v dd v output voltage low v ol i ol = 1.6 ma 0.45 v output voltage high v oh i oh = C0.4 ma v dd C 1.0 v input current i i ea, p10/nmi; 0 v i v dd 20 m a input leakage current i li except ea, p10/nmi; 0 v i v dd 10 m a output leakage current i lo 0 v o v dd 10 m a v th current i th 0 v v th v dd 0.5 1.0 ma v dd supply current i dd1 operating mode m pd70325-8 65 120 ma m pd70325-10 95 130 ma i dd2 halt mode m pd70325-8 25 50 ma m pd70325-10 30 55 ma i dd3 stop mode 10 30 m a parameter symbol test conditions min. max. unit x1 input cycle time t cyx 62 250 ns x1 input high-/low-level width t wxh , t wxl 20 ns x1 input rise/fall time t xr , t xf 20 ns clkout output cycle time t cyk f x /2, t = t cyk 125 2000 ns clkout output high-/low-level width t wkh , t wkl 0.5t C 15 ns clkout output rise/fall time t kr , t kf 15 ns input rise/fall time t ir , t if except reset, nmi, 20 ns x1 and x2 t irs , t ifs reset, nmi 30 ns output rise/fall time t or , t of except clkout 20 ns www.datasheet.co.kr datasheet pdf - http://www..net/ 52 m pd70325 parameter symbol test conditions min. max. unit address delay time from clkout t dka 15 90 ns data input delay time from address t dadr (n + 1.5)t C 70 ns data delay time from mreq ? t dmrd (n + 1)t C 60 ns data delay time from mstb ? t dmsd (n + 0.5)t C 60 ns mstb ? delay time from mreq ? t dmrms 0.5t C 35 0.5t + 35 ns mreq low-level width t wmrl (n + 1)t C 30 (n + 1)t + 30 ns address hold time (from mreq )t hma 0.5t C 30 ns data input hold time (from mreq )t hmdr 0ns control signal recovery time t rvc t C 25 ns data output delay time from address t dadw 0.5t C 35 0.5t + 50 ns address setup time (to mreq ? )t damr 0.5t C 30 ns address setup time (to mstb ? )t dams t C 30 ns mstb low-level width t wmsl (n + 0.5)t C 30 (n + 0.5)t + 30 ns data output setup time (to mstb )t sdm (n + 1)t C 50 ns data output hold time (from mstb )t hmdw 0.5t C 30 ns address setup time (to iostb ? )t dais 0.5t C 30 ns data delay time from iostb ? t disd (n + 1)t C 60 ns iostb low-level width t wisl (n + 1)t C 30 ns address hold time (from iostb )t hisa 0.5t C 30 ns data input hold time (from ioreq )t hisdr 0ns data output setup time (to iostb )t sdis (n + 1)t C 50 ns data output hold time (from iostb )t hisdw 0.5t C 30 ns dmarq setup time (to mreq ? )t sdadq demand release mode, n 2 (n C 1)t C 50 ns dmarq hold time (from dmaak ? )t hdadq demand release mode 0 ns dmaak output low-level width t wdmrl read operation (n + 1.5)t C 30 ns tc ? delay time from dmaak ? t ddatc 0.5t + 50 ns tc low-level width t wtcl (n + 2)t C 30 ns dmaak output low-level width t wdmwl write operation (n + 1)t C 30 ns address setup time (to refrq ? )t darf 0.5t C 30 ns refrq low-level width t wrfl (n + 1)t C 30 ns address hold time (from refrq )t hrfa 0.5t C 30 ns reset low-level width t wrsl1 stop mode release/ 30 ms power-on reset t wrsl2 system reset 5 m s ready setup time t scry0 n 2 t C 100 ns (to mreq ? , iostb ? ) t scry n 3 (n C 1)t C 100 ns remark n indicates the number of wait states. no wait is n = 0. www.datasheet.co.kr datasheet pdf - http://www..net/ 53 m pd70325 parameter symbol test conditions min. max. unit ready hold time t hcry0 n = 2 t ns (from mreq ? , iostb ? ) t hcry n 3 (n C 1)t ns t hcry1 n 3 (n C 2)t ns hldrq setup time (to clkout )t shqk 30 ns hldak ? delay time from clkout t dkha 15 80 ns hldak ? delay time from bus float t cfha t C 50 ns bus output delay time from hldak t dhac t C 50 ns hldak delay time from hldrq ? t dhqha 3t + 160 ns bus output delay time from hldrq ? t dhqc 3t + 30 ns hldrq low-level width t whql 1.5t ns hldak low-level width t whal tns int, dmarq setup time (to clkout )t siqk 30 ns int, dmarq high-/low-level width t wiqh , t wiql 8t ns poll setup time (to clkout )t splk 30 ns nmi high-/low-level width t wnih , t wnil 5 m s cts low-level width t wctl 2t ns int setup time (to clkout )t sirk 30 ns intak ? delay time from clkout ? t dkia 15 80 ns int hold time (from intak ? )t hiaiq 0ns intak low-level width t wial 2t C 30 ns intak high-level width t wiah t C 30 ns data delay time from intak ? t diad 2t C 130 ns data hold time (from intak )t hiad 0 0.5t ns sck0 cycle time t cytk 1000 ns sck0 high-/low-level width t wsth , t wstl 450 ns txd delay time from sck0 ? t dtkd 210 ns txd hold time (from sck0 ? )t htkd 20 ns cts0 cycle time t cyrk 1000 ns cts0 high-/low-level width t wsrh , t wsrl 420 ns rxd setup/hold time (to/from cts0 )t srdk , t hkrd 80 ns remark n indicates the number of wait states. no wait is n = 0. www.datasheet.co.kr datasheet pdf - http://www..net/ 54 m pd70325 (2) m pd70325-10 (t a = C10 to +70 c, v dd = +5.0 v 5%) parameter symbol test conditions min. max. unit x1 input cycle time t cyx 49 250 ns x1 input high-/low-level width t wxh , t wxl 16 ns x1 input rise/fall time t xr , t xf 15 ns clkout output cycle time t cyk f x /2, t = t cyk 100 2000 ns clkout output high-/low-level width t wkh , t wkl 0.5t C 12 ns clkout output rise/fall time t kr , t kf 12 ns input rise/fall time t ir , t if except reset, nmi, 20 ns x1 and x2 t irs , t ifs reset, nmi 30 ns output rise/fall time t or , t of except clkout 15 ns address delay time from clkout t dka 15 75 ns data input delay time from address t dadr (n + 1.5)t C 60 ns data delay time from mreq ? t dmrd (n + 1)t C 50 ns data delay time from mstb ? t dmsd (n + 0.5)t C 50 ns mstb ? delay time from mreq ? t dmrms 0.5t C 20 0.5t + 30 ns mreq low-level width t wmrl (n + 1)t C 25 (n + 1)t + 25 ns address hold time (from mreq )t hma 0.5t C 30 ns data input hold time (from mreq )t hmdr 0ns control signal recovery time t rvc t C 25 ns data output delay time from address t dadw 0.5t C 30 0.5t + 50 ns address setup time (to mreq ? )t damr 0.5t C 30 ns address setup time (to mstb ? )t dams t C 30 ns mstb low-level width t wmsl (n + 0.5)t C 25 (n + 0.5)t + 25 ns data output setup time (to mstb )t sdm (n + 1)t C 50 ns data output hold time (from mstb )t hmdw 0.5t C 30 ns address setup time (to iostb ? )t dais 0.5t C 30 ns data delay time from iostb ? t disd (n + 1)t C 50 ns iostb low-level width t wisl (n + 1)t C 25 ns address hold time (from iostb )t hisa 0.5t C 30 ns data input hold time (from ioreq )t hisdr 0ns data output setup time (to iostb )t sdis (n + 1)t C 50 ns data output hold time (from iostb )t hisdw 0.5t C 30 ns dmarq setup time (to mreq ? )t sdadq demand release mode, n 2 (n C 1)t C 50 ns dmarq hold time (from dmaak ? )t hdadq demand release mode 0 ns dmaak output low-level width t wdmrl read operation (n + 1.5)t C 25 ns tc ? delay time from dmaak ? t ddatc 0.5t + 35 ns tc low-level width t wtcl (n + 2)t C 25 ns dmaak output low-level width t wdmwl write operation (n + 1)t C 25 ns address setup time (to refrq ? )t darf 0.5t C 30 ns refrq low-level width t wrfl (n + 1)t C 25 ns address hold time (from refrq )t hrfa 0.5t C 30 ns remark n indicates the number of wait states. no wait is n = 0. www.datasheet.co.kr datasheet pdf - http://www..net/ 55 m pd70325 parameter symbol test conditions min. max. unit reset low-level width t wrsl1 stop mode release/ 30 ms power-on reset t wrsl2 system reset 5 m s ready setup time t scry0 n 2 t C 80 ns (to mreq ? , iostb ? ) t scry n 3 (n C 1)t C 80 ns ready hold time t hcry0 n = 2 t ns (from mreq ? , iostb ? ) t hcry n 3 (n C 1)t ns t hcry1 n 3 (n C 2)t ns hldrq setup time (to clkout )t shqk 25 ns hldak ? delay time from clkout t dkha 15 70 ns hldak ? delay time from bus float t cfha t C 35 ns bus output delay time from hldak t dhac t C 35 ns hldak delay time from hldrq ? t dhqha 3t + 160 ns bus output delay time from hldrq ? t dhqc 3t + 30 ns hldrq low-level width t whql 1.5t ns hldak low-level width t whal tns int, dmarq setup time (to clkout )t siqk 25 ns int, dmarq high-/low-level width t wiqh , t wiql 8t ns poll setup time (to clkout )t splk 25 ns nmi high-/low-level width t wnih , t wnil 5 m s cts low-level width t wctl 2t ns int setup time (to clkout )t sirk 25 ns intak ? delay time from clkout ? t dkia 15 70 ns int hold time (from intak ? )t hiaiq 0ns intak low-level width t wial 2t C 25 ns intak high-level width t wiah t C 25 ns data delay time from intak ? t diad 2t C 100 ns data hold time (from intak )t hiad 0 0.5t ns sck0 cycle time t cytk 1000 ns sck0 high-/low-level width t wsth , t wstl 450 ns txd delay time from sck0 ? t dtkd 210 ns txd hold time (from sck0 ? )t htkd 20 ns cts0 cycle time t cyrk 1000 ns cts0 high-/low-level width t wsrh , t wsrl 420 ns rxd setup/hold time (to/from cts0 )t srdk , t hkrd 80 ns remark n indicates the number of wait states. no wait is n = 0. www.datasheet.co.kr datasheet pdf - http://www..net/ 56 m pd70325 comparator characteristics m pd70325-8 (t a = C10 to +70 c, v dd = +5.0 v 10%) m pd70325-10 (t a = C10 to +70 c, v dd = +5.0 v 5%) parameter symbol test conditions min. typ. max. unit comparator accuracy v acomp 100 mv threshold voltage v th 0v dd + 0.1 v compare time t comp 64 65 t cyk pt input voltage v ipt 0v dd v data memory stop mode low supply voltage data holding characteristics (t a = C10 to +70 c) parameter symbol test conditions min. max. unit data hold supply voltage v dddr 2.5 5.5 v v dd rise/fall time t rvd , t fvd 200 m s www.datasheet.co.kr datasheet pdf - http://www..net/ 57 m pd70325 data holding timing ac test input waveform (except reset, nmi, x1 and x2) ac test input waveform (reset, nmi, x1 and x2) ac test output test points output load condition: 100 pf load condition caution when the load capacity exceeds 100 pf depending on the circuit configuration, make the load capacity of this device less than 100 pf by inserting a buffer, etc. 90% 10% v dddr t fvd t rvd 2.2 v 0.8 v t if test points 2.2 v 0.8 v t ir 0.8 v dd 0.8 v t ifs test points 0.8 v dd 0.8 v t irs 2.2 v 0.8 v test points 2.2 v 0.8 v dut c l = 100 pf www.datasheet.co.kr datasheet pdf - http://www..net/ 58 m pd70325 clock timing t cyx t wxh t wxl t xf t xr 0.8 v dd 0.8 v x1 t cyk t wkh t wkl t kf t kr 2.2 v 0.8 v clkout poll input timing t splk t splk clkout poll cts0 and cts1 input timing t wctl cts0 and cts1 www.datasheet.co.kr datasheet pdf - http://www..net/ 59 m pd70325 interrupt input/dma input timing clkout nmi note t siqk t wnih t wiqh t wnil t wiql t siqk note intp0 to intp2, dmarq0 to dmarq1 reset input timing when stop mode is released/at power-on reset: note clkout signal is output after clkout output is set. when system is reset: note clkout output is set to input port by reset input. t wrsl1 hi-z clkout note reset t wrsl2 hi-z clkout note reset www.datasheet.co.kr datasheet pdf - http://www..net/ 60 m pd70325 ready timing when 2 wait states are inserted: when (n C 2) extra wait states are inserted [n 3]: notes 1. in case of memory cycle 2. in case of i/o cycle caution the wait state insertion by the external ready signal is necessary to make the value of wait control register (wtc) 11 (2 waits + insertion state by ready pin). t hcry0 t scry0 t1 taw taw t2 mreq note 1 iostb note 2 ready t1 taw taw t2 t hcry1 t scry t hcry tw (n ?2) ready t scry0 mreq note 1 iostb note 2 www.datasheet.co.kr datasheet pdf - http://www..net/ 61 m pd70325 t cytk t wstl t wsth t dtkd t htkd sck0 txd t cyrk t wsrl t wsrh t srdk cts0 rxd t hkrd serial operation when transmitting data in i/o interface mode when receiving data in i/o interface mode www.datasheet.co.kr datasheet pdf - http://www..net/ 62 m pd70325 read operation t cyk t dka t dka t dadr hi-z hi-z t hma t hmdr t damr t dmrd t wmrl t rvc t dmrms t dmsd t dams t wmsl clkout a19 to a0 d7 to d0 r/ w mreq mstb iostb refrq dmaak1 to dmaak0 www.datasheet.co.kr datasheet pdf - http://www..net/ 63 m pd70325 t cyk hi-z hi-z t dka t dka t dadw t hma t hmdw t damr t wmrl t rvc t dmrms t dams t wmsl clkout a19 to a0 d7 to d0 r/ w mreq mstb iostb refrq dmaak1 to dmaak0 t sdm write operation www.datasheet.co.kr datasheet pdf - http://www..net/ 64 m pd70325 i/o read timing t cyk t dka t dka t dadr hi-z h hi-z t hisa t hisdr t disd clkout a19 to a0 d7 to d0 r/ w mreq mstb iostb refrq dmaak1 to dmaak0 t dais t wisl t rvc www.datasheet.co.kr datasheet pdf - http://www..net/ 65 m pd70325 i/o write timing t cyk t dka t dka t dadw hi-z h hi-z t hisa t hisdw clkout a19 to a0 d7 to d0 r/ w mreq mstb iostb refrq dmaak1 to dmaak0 t sdis t dais t wisl t rvc www.datasheet.co.kr datasheet pdf - http://www..net/ 66 m pd70325 dma (i/o ? memory) timing t cyk t dka t hma t damr t wmrl hi-z t rvc t dmrms t dams t wmsl clkout a19 to a0 d7 to d0 r/ w mreq mstb iostb dmaak1 to dmaak0 t sdadq t hdadq t wdmrl t ddatc t wtcl dmarq1 to dmarq0 tc1 to tc0 www.datasheet.co.kr datasheet pdf - http://www..net/ 67 m pd70325 dma (memory ? i/o) timing t cyk t dka t hma t damr hi-z t wmrl t rvc t dams t wmsl clkout a19 to a0 d7 to d0 r/ w mreq mstb iostb dmaak1 to dmaak0 t sdadq t hdadq t wdmwl t ddatc t wtcl dmarq1 to dmarq0 tc1 to tc0 www.datasheet.co.kr datasheet pdf - http://www..net/ 68 m pd70325 refresh timing t cyk t dka hi-z h clkout a19 to a0 d7 to d0 r/ w mreq mstb iostb refrq dmaak1 to dmaak0 t rvc t hrfa t darf t wrfl www.datasheet.co.kr datasheet pdf - http://www..net/ 69 m pd70325 hold request/acknowledge timing normal mode releasing hold mode at refreshing time note a19 to a0, d7 to d0, mreq, mstb, iostb, r/w external interrupt request/acknowledge timing t shqk t shqk t dkha hi-z t whql t cfha t whal t dhqha t dhac clkout hldrq note hldak t shqk t dkha t whql hi-z t dhqc clkout hldrq note hldak clkout int d0 to d7 t sirk t hiaiq t dkia hi-z t wial t rvc t wiah t diad t hiad t rvc mreq iostb intak www.datasheet.co.kr datasheet pdf - http://www..net/ 70 m pd70325 clock synchronization timing the v25 family is designed to create access signals to memory and i/o, based on the mreq signal and iostb signal. when v25 family products are connected with memory and i/o, design is possible even if there are no ac characteristics based on the clock. the clock synchronization timing shown below is for executing accurate ready input control using the system clock. (1) m pd70325-8 (t a = C10 to +70 c, v dd = +5.0 v 10%) parameter symbol test conditions min. max. unit data delay time from clkout t dkd 65 115 ns data input setup time t sdk 15 ns data input hold time t hkd 40 ns mreq delay time t dkmr 10 55 ns iostb delay time t dkis 10 55 ns ready setup time t sryk 20 ns ready hold time t hkry 40 ns (2) m pd70325-10 (t a = C10 to +70 c, v dd = +5.0 v 5%) parameter symbol test conditions min. max. unit data delay time from clkout t dkd 60 110 ns data input setup time t sdk 10 ns data input hold time t hkd 35 ns mreq delay time t dkmr 10 55 ns iostb delay time t dkis 10 55 ns ready setup time t sryk 15 ns ready hold time t hkry 40 ns www.datasheet.co.kr datasheet pdf - http://www..net/ 71 m pd70325 ready timing when 2 wait states are inserted: when 1 extra wait state is inserted: t sryk t hkry t1 taw taw t2 clkout a19 to a0 mreq iostb ready t sryk t1 taw tw t2 clkout a19 to a0 mreq iostb ready taw t sryk t hkry t hkry www.datasheet.co.kr datasheet pdf - http://www..net/ 72 m pd70325 memory read operation memory write operation clkout a19 to a0 d7 to d0 mreq t cyk r/w t sdk t hkd t dka t dka hi-z hi-z t dkmr t dkmr t dkmr clkout a19 to a0 d7 to d0 mreq t cyk r/w t dkd t dka t dka hi-z hi-z t dkmr t dkmr t dkmr www.datasheet.co.kr datasheet pdf - http://www..net/ 73 m pd70325 i/o read timing i/o write timing clkout a19 to a0 d7 to d0 mreq t cyk r/w t hkd t dka t dka hi-z hi-z t dkmr iostb t dkis t dkis t dkis t sdk clkout a19 to a0 d7 to d0 mreq t cyk r/w t dka t dka hi-z hi-z t dkmr iostb t dkis t dkis t dkis t dkd www.datasheet.co.kr datasheet pdf - http://www..net/ 74 m pd70325 4. package drawings 94 pin plastic qfp ( 20) item millimeters inches f 1 f 2 i 1.6 0.8 0.15 q 0.063 0.031 0.006 s94gj-80-5bg-3 note each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. c 20.0 0.2 0.787 m 0.15 0.006 0.1 0.1 0.004 0.004 +0.004 e0.003 +0.009 e0.008 a 23.2 0.4 0.913 h 0.35 0.10 0.014 +0.004 e0.005 l 0.8 0.2 0.031 +0.009 e0.008 n 0.10 0.004 p 3.7 0.146 s 4.0 max. 0.158 max. +0.10 e0.05 b 20.0 0.2 0.787 +0.009 e0.008 +0.017 e0.016 j 0.8 (t.p.) 0.031 (t.p.) r5 5 5 5 d 23.2 0.4 0.913 +0.017 e0.016 g 1 g 2 1.6 0.8 0.063 0.031 k 1.6 0.2 0.063 0.008 a b g 1 hi j c d p n k l m detail of lead end f 2 f 1 m 71 72 47 94 24 23 48 1 g 2 s q r www.datasheet.co.kr datasheet pdf - http://www..net/ 75 m pd70325 84 pin plastic qfj ( 1150 mil) p84l-50a3-2 item millimeters inches a b c d f g h i j k 30.2 0.2 29.28 0.6 4.4 0.2 2.8 0.2 29.28 1.189 0.008 0.076 0.024 0.110 0.035 min. 1.153 note m n 0.12 0.40 0.10 3.4 0.9 min. 0.005 0.016 +0.004 e0.005 each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. 0.134 0.173 1.153 1.27 (t.p.) 0.050 (t.p.) p 28.20 0.20 1.110 1.189 0.008 30.2 0.2 1.94 0.15 q 0.15 0.006 t r 0.8 r 0.031 +0.009 e0.008 e u 0.20 0.008 +0.10 e0.05 +0.004 e0.002 +0.009 e0.008 +0.007 e0.006 +0.009 e0.008 c a 84 b 1 t n q m k i m u h e g j f d www.datasheet.co.kr datasheet pdf - http://www..net/ 76 m pd70325 5. recommended soldering conditions the following conditions must be met when soldering this product. for more details, refer to our document semiconductor device mounting technology manual (c10535e) . please consult with our sales office when using other soldering process or under different soldering conditions. table 5-1. surface mount type soldering conditions (1) m pd70325gj-8-5bg : 94-pin plastic qfp (20 20 mm) m pD70325GJ-10-5bg : 94-pin plastic qfp (20 20 mm) soldering process soldering conditions symbol infrared ray reflow package peak temperature: 235 c, reflow time: 30 seconds or less (at 210 c ir35-367-3 or higher), number of reflow processes: 3 or less exposure limit note : 7 days (36 hours pre-baking is required at 125 c afterwards) vps package peak temperature: 215 c, reflow time: 40 seconds or less (at 200 c vp15-367-3 or higher), number of reflow processes: 3 or less exposure limit note : 7 days (36 hours pre-baking is required at 125 c afterwards) wave soldering solder temperature: 260 c or below, flow time: 10 seconds or less, ws60-367-1 number of flow processes: 1 exposure limit note : 7 days (36 hours pre-baking is required at 125 c afterwards) pre-heating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c or below, method flow time: 3 seconds or less (per side of device) (2) m pd70325l-8 : 84-pin plastic qfj (1150 1150 mil) m pd70325l-10 : 84-pin plastic qfj (1150 1150 mil) soldering process soldering conditions symbol vps package peak temperature: 215 c, reflow time: 40 seconds or less (at 200 c vp15-162-1 or higher), number of reflow processes: 1 exposure limit note : 2 days (16 hours pre-baking is required at 125 c afterwards) partial heating pin temperature: 300 c or below, method flow time: 3 seconds or less (per side of device) note exposure limit before soldering after dry-pack package is opened. storage conditions: 25 c and relative humidity at 65% or less. caution use of more than one soldering process should be avoided (except for partial heating method). www.datasheet.co.kr datasheet pdf - http://www..net/ 77 m pd70325 [memo] www.datasheet.co.kr datasheet pdf - http://www..net/ 78 m pd70325 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function. www.datasheet.co.kr datasheet pdf - http://www..net/ 79 m pd70325 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. cumbica-guarulhos-sp, brasil tel: 011-6465-6810 fax: 011-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j97. 8 www.datasheet.co.kr datasheet pdf - http://www..net/ m pd70325 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard : computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific : aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 related documents v25+, v35+ user's manual hardware ieu-706 (japanese version) v25, v35 family user's manual instructions u12120j (japanese version) reference document electrical characteristics for microcomputer iei-601 (japanese version) the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. v25, v25+, v35, and v35+ are trademarks of nec corporation. www.datasheet.co.kr datasheet pdf - http://www..net/ |
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